Previously, we compiled semiwiki's earlier reports on TSMC's advanced technology (see "The latest sharing of TSMC's technology: Huge amount of information" for details). Recently, they have updated their reports on TSMC’s latest packaging, which we also share with you here.
Readers familiar with TSMC will know that the police foundry giant has merged its 2.5D and 3D packaging products into one brand - "3D Fabric". In line with their expectations, future customers will pursue both options to provide dense, heterogeneous integration of system-level functionality—for example, “front-end” 3D vertical assembly combined with “back-end” 2.5D integration.
Technically speaking, the 2.5D integration of the SoC with the “3D” high-bandwidth memory HBM stack is already a combined product. As shown in the figure above, TSMC is envisioning richer topology combinations in the future, combining 3D SoIC with 2.5D CoWoS/InFO as part of very complex heterogeneous system designs.
As with the process technology demos at the workshop, the updates to the packaging technology are very simple – a sign of the success of its roadmap, which simply requires continued execution, with a few specific areas representing new directions we’ll highlight below. .
Of particular note is TSMC’s investment in an advanced system integration fab that will support 3D Fabric products, providing complete assembly and test manufacturing capabilities. According to TSMC, the world's first fully automated 3D Fabric advanced packaging plant in Zhunan is expected to start production in the second half of this year.
Why focus on advanced packaging
In everyone's consistent understanding, TSMC is actually engaged in the business of wafer foundry. But in the new century, whether it is TSMC, , Samsung, or even Intel, advanced packaging is regarded as a major focus of the company. This is mainly due to the conflict between the growing performance requirements and the gradual failure of Moore's Law and . The result of evolution.
As reported by semiwiki, Moore's Law is no longer cost-effective for many other applications, especially for integrating heterogeneous functions, multi-chip modules (MCM) and system-in-package (System in PackageSiP) "Moore than Moore" technologies have become an alternative to integrating large amounts of logic and memory, analog, MEMS, etc. into (subsystem) solutions. However, these approaches are still very customer-specific and can take a lot of development time and cost.
Looking at the history of chip development, in fact, the concept of advanced packaging has existed for decades. Compromising is one way to advance chip design by assembling different and advanced chips in packages. Today, this concept is sometimes called heterogeneous integration. Still, due to cost reasons, advanced packaging is mainly used in high-end, niche-market applications.
But that may change soon. Because IC scaling is the traditional way to advance designs, it shrinks the different chip functions at each node and packages them onto a monolithic chip. However, IC scaling is becoming too expensive for many, and the benefits per node are diminishing.
While scaling remains an option for new designs, the industry is looking at alternatives, including advanced packaging. What is changing is that the industry is developing new advanced packaging types or extending existing technologies. The motivation behind the
high-level packaging remains the same. Instead of cramming all chip functions on the same chip, break them down and integrate them into a single package. This is said to reduce costs and provide better yields. Another goal is to bring the chips closer to each other. Many advanced packaging brings memory closer to the processor, allowing faster access to data with lower latency.
This sounds simple, but there are several challenges here. Additionally, there is no one package type that meets all needs. In fact, chip customers face a variety of choices. Among them: Fan-out (integrated dies and components in a wafer-level package), 2.5D/3D (chips placed side by side or on top of each other in a package) and 3D-IC: (memory stacked on top of memory, stacked on top of logic or Logically stacking logic) becomes three common choices.
Additionally, the industry is also pursuing a concept called Chiplets, which supports 2.5D/3D technology. The idea is that you have a choice of modular chips or chiplets in the library. They are then integrated into a package and connected using a die-to-die interconnect scheme.
On the TSMC side, in order to meet market demand for new multi-chip IC packaging solutions, they have also collaborated with their OIP partners to develop advanced IC packaging technologies to provide economical solutions to enable integration beyond Moore's Law.
In 2012, TSMC and Xilinx launched the largest FPGA at the time, which consisted of four identical 28 nm FPGA chips mounted side by side on a silicon interposer. They also developed through silicon vias (TSVs), microbumps and re-distribution-layers (RDL) to connect these building blocks to each other. TSMC named this integrated circuit packaging solution CoWoS (Chip-on-Wafer-on-Substrate) based on its structure. This building block-based and EDA-enabled packaging technology has become the de facto industry standard for high-performance and high-power designs.
TSMC announced InFO (Integrated FanOut technology) technology in 2017. It uses polyamide film instead of the silicon interposer in CoWoS, thereby reducing the unit cost of and packaging height, both of which are important criteria for mobile application success. TSMC has shipped a large number of InFO designs for smartphones.
TSMC launched system on integrated chip system (SoIC) technology in 2019. With front-end (fab) equipment, TSMC can very precisely align and then compression-bond the design using many narrow-pitch copper pads to further minimize form factor, interconnect capacitance and power. These two technologies,
, gradually evolved into today's 3D Fabric.
The latest update in 2022
As shown above, according to TSMC’s plan, their packaging technologies now include 2.5D and 3D. Let’s take a look at their 2.5D first. According to reports, TSMC now has two types of 2.5D packaging technologies - "chip-on-wafer-on-substrate" (CoWoS: chip-on-wafer-on-substrate) and "InFO: integrated fanout". (Note that in the image above, some InFO products are represented by TSMC as "2D.")
The key move for both technologies is to continue to expand the maximum package size to allow for the integration of more dies (and HBM stacks). For example, fabricating interconnect layers on a silicon interposer (CoWoS-S) requires “stitching” multiple lithography exposures—the goal is to increase the interposer size by a multiple of the maximum reticle size.
first looks at CoWoS. According to reports, TSMC CoWoS has expanded to provide three different interposer technologies ("wafers" in CoWoS):
1.CoWoS-S: According to TSMC, in this packaging mode, silicon is used Interposer, based on existing silicon lithography and redistribution layer processing
▪️ Volume production since 2012, with over 100 products supplied to over 20 customers to date
▪️ Interposer integrates embedded "trench" capacitors
▪️ 3x maximum reticle size in development – supports design configurations with 2 large SoCs and 8 HBM3 memory stacks, and eDTC1100 (1100nF/mm**2)
2.CoWoS-R: in this package mode , uses organic interposer to reduce cost
▪️ Up to 6 interconnect redistribution layers, 2um/2um L/S
▪️ 4x mask size, supports one SoC and 2 HBM2 stacks, in 55mmX55mm package; 2.1X mask Dimensions under development, 2 SoCs and 2HBM2 in 85mm L/S pitch)
▪️ 2X reticle size supports 2 SoCs with 6 HBM2 stacks (2023);
▪️ 4X reticle size is in development to support 12 HBM3 stacks (2024)
TSMC emphasizes that they are working with The HBM standards group collaborates on the physical configuration of HBM3 interconnect requirements for CoWoS implementations.(For stack definitions, the HBM3 standard appears to have settled on the following: 4GB capacity (four 8Gb dies) to 64GB (16 32Gb dies); 1024-bit signaling interface; up to 819GBps bandwidth.) These upcoming CoWoS configurations have Multiple HBM3 stacks will provide huge memory capacity and bandwidth.
Additionally, in anticipation of greater power consumption in upcoming CoWoS designs, TSMC is investigating suitable cooling solutions, including improving the thermal interface material (TIM) between the chip and package, and transitioning from air cooling to immersion cooling .
After introducing CoWoS, let's look at its InFO packaging technology.
It is understood that this packaging technology is to encapsulate the die in the epoxy resin "wafer" after placing it in the correct (face down) direction on the temporary carrier. A redistribution interconnect layer is added to the reconstructed silicon surface. The package bumps are then connected directly to the redistribution layer.
According to TSMC, the company’s package has several topologies: InFO_PoP, InFO_oS and InFO_B.
As shown in the figure below, InFO_PoP represents the package-on-package configuration, focusing on the integration of DRAM packaging and basic logic chips. Bumps on the top die of the DRAM utilize through-InFO vias (TIVs) to reach the redistribution layer.
TSMC said that InFO_PoP is mainly used for mobile platforms, and since the interview in 2016, chip shipments of this package have exceeded 1.2 billion. According to TSMC, in the current InFO_PoP mode, its DRAM package is a custom design and therefore can only be manufactured at TSMC. To this end TSMC is developing an alternative InFO_B topology that adds existing (LPDDR) DRAM packaging on top and allows external contract manufacturers to provide assembly.
InFO_oS (on-substrate) can package multiple dies, and the redistribution layer and its microbumps are connected to the substrate through TSVs.
This is a technology in production for over 5 years, focused on HPC customers. In technical detail, the package has 5 RDL layers on the substrate with 2um/2um L/S. This allows the substrate to achieve larger package sizes, currently 110mm X 110mm. According to TSMC, the company plans to provide a larger size in the future - 130um C4 bump pitch
As for InFO_M, it is a replacement for InFO_oS, with multiple packaging dies and redistribution layers, without the need for additional substrate + TSV (can achieve 500mm² packaged and will be produced in 2H2022).
After introducing TSMC's 2.5D packaging, we entered their 3D packaging world. Among them, there is a 3D stacked packaging technology called InFO-3D, which utilizes micro-bump chips vertically integrated with redistribution layers and TIV, focusing on mobile platforms.
As shown in the figure, TSMC also has a more advanced vertical die stacking 3D topology packaging series - called "system on integrated chip" (SoIC). It utilizes direct copper bonding between die and can achieve a very high pitch.
According to TSMC, the company has two SoIC products - "wafer-on-wafer" (WOW) and "chip-on-wafer" (COW). Among them, the WOW topology integrates a complex SoC die on the wafer, providing a deep trench capacitor (DTC) structure for optimal decoupling. The more general COW topology stacks multiple SoC dies.
The process technologies suitable for SoIC assembly are shown in the table below.
According to TSMC, the company’s 3DFabric design support also includes 3Dblox. As shown in the upper right corner of the 3D Fabric image above, TSMC is envisioning complex system-in-package design implementations combining 3D SoIC and 2.5D technologies.
As mentioned above, this design flow is very complex and requires advanced thermal, timing, and SI/PI analysis flows (which can also handle the volume of model data). To support the development of these system-level designs, TSMC is collaborating with EDA vendors on three main design flow initiatives:
which first includes using a coarse-grained plus fine-grained approach to obtain improved thermal analysis.
Secondly, TSMC and EDA giants are also cooperating on hierarchical static timing analysis. Let individual dies be represented by abstract models to reduce the complexity of multi-corne data analysis.
Finally, TSMC and the EDA giant also cooperated on the front-end design partition. 2. To help accelerate the front-end design division of complex systems, TSMC has also implemented a program called "3Dblox".
According to TSMC, the company’s goal with this plan is to decompose the entire physical packaging system into modular components and then integrate them. As shown in the figure, the module categories of the plan are: bumps/bonds, vias, caps, interposers and die.
With this program, these modules will be integrated into any SoIC, CoWoS or InFO packaging technology.
Of particular note is that TSMC is working to enable 3D Fabric design to use a variety of EDA tools - that is, using one EDA vendor tool to complete the physical design, and (potentially) using a different EDA vendor product to Supports timing analysis, signal integrity/power integrity analysis, and thermal analysis.
3Dblox appears to be taking the concept of "reference flows" for SoCs to the next level, with TSMC pushing for interoperability between EDA vendor data models and formats. The overall flow capability of 3Dblox will be launched in the third quarter of 2022. (Preliminary steps—namely, automatically routing redistributed signals on InFO—will be the first feature released.)
Clearly, TSMC has a strong focus on advanced packaging technology development and (especially) due to expected growth in 2.5D and 3D configurations. Significant investments have been made in new manufacturing facilities. The transition from HBM2/2e to HBM3 memory stacks will bring significant performance benefits to system designs using CoWoS 2.5 technology. Mobile platform customers will expand the diversity of InFO multi-chip designs. Adoption of complex 3DFabric designs that combine 3D and 2.5D technologies will undoubtedly increase as well, leveraging TSMC's efforts to "modularize" design elements to accelerate system partitioning, as well as their efforts to enable the application of a wide range of EDA tools/flows. .
Fundamentals of packaging technology
According to TSMC’s definition, front-end chip stacking technologies such as CoW (chip-on-wafer) and WoW (wafer-on-wafer) are collectively called “SoIC”, that is, System of Integrated Chips ). The goal of these technologies is to stack silicon dies together without using the "bumps" seen on back-end integration options. Here, the SoIC design is actually creating the bonding interface so that the silicon can sit on top of the silicon as if it were a single piece of silicon.
According to TSMC’s official introduction, the company’s SoIC service platform provides innovative front-end 3D chip-to-chip stacking technology for reintegrating small chips divided from system-on-chip (SoC). The resulting integrated chip outperforms the original SoC in terms of system performance. It also provides the flexibility to integrate other system functions. TSMC noted that the SoIC service platform can meet the growing computing, bandwidth and latency requirements in cloud, network and edge applications. It supports CoW and WoW solutions, which provide excellent design flexibility when mixing and matching different chip functions, sizes and technology nodes.
Specifically, TSMC's SoIC technology is a very powerful way to stack multiple dies into "3D building blocks" (also known as "3D Chiplets").
Today, SoICs are capable of approximately 10,000 interconnects per square millimeter of space between vertically stacked chips. But the development work towards 1 million interconnects per square millimeter is underway. 3D-IC enthusiasts have been looking for an IC packaging method that can achieve such fine interconnections, further reduce form factor, eliminate bandwidth limitations, simplify thermal management in die stacks, and integrate large, highly parallel systems into them.
According to TSMC, one of the benefits of SoIC is its thermal performance. However, the downside to these SoIC technologies is that the stacked designs must be co-designed with each other. Yet micro-bumping technologies such as EMIB do so in a way that technically connects a series of chips together. Using SoIC technologies like COW and WOWO, the design is fixed from the beginning.
Despite this, TSMC is still keen to improve its SoIC chip stacking capabilities.According to TSMC's plans, this is a key technology for their future integration, which goes beyond the past implementation of interposers or chip stacking because it allows silicon chips to be stacked without using any micro-bumps, and directly The metal layer of silicon is aligned and bonded to the silicon chip. Another relatively simple solution in the
package is to connect two silicon chips in one package. Typically, this is done with two pieces of silicon side by side, with a variety of connections. The one most people are most familiar with is the interposer method, which places a large piece of silicon underneath all the interconnected dies and is a faster routing method than simply running traces through the PCB package.
Similarly, another approach is to embed an interposer in the PCB just to connect one specific die to another (this is what Intel calls its Embedded Multi-Die Interconnect Bridge, or EMIB).
The third is a direct vertical stacking of die to die, however, this is different from the SoIC implementation mentioned above due to the use of microbumps between the two pieces of silicon - SoIC uses bonding. Virtually all implementations in TSMC's second half products are micro-bump based, as this allows for better mixing and matching between different chips after each chip is manufactured, but doesn't get the density that SoIC offers or power consumption advantage.
That's why it's called "backend" high-level packaging. GPU with HBM function is implemented in this way.
Many HBM-enabled GPUs have one GPU die, several HBM dies, all placed on top of the interposer. The GPU and HBM are manufactured by different companies (even different HBMs may be used), and the silicon interposer may be manufactured elsewhere as well. This silicon interposer can be passive (containing no logic, just routing from die to die) or active, and can be designed to enable better network interconnection between chips if needed, Although this means that the interposer consumes power.
TSMC’s GPU interposer-like strategy has been called CoWoS (chip-on-wafer-on-substrate) in the past. As part of 3DFabric, divided in terms of implementation, CoWoS now has three variants:
The standard that everyone is familiar with is called CoWoS-S, where S stands for Silicon Interposer. The limitation of CoWoS-S is the size of the interposer, which is typically manufactured on a 65nm manufacturing process or similar. Since the interposer is a monolithic piece of silicon, it must be manufactured similarly, and as we enter the era of chiplets, customers are demanding larger and larger interposers, which means TSMC must be able to manufacture them (and deliver them in high yields).
Traditional chips are limited by the size of the reticle, which is a fundamental limitation within the machine, that is, the size of a layer that can be "printed" on a single instance. To make die-size products possible, TSMC has been developing multi-reticle size interposer technology to make these products larger. Based on TSMC's own roadmap, we expect CoWoS implementations in 2023 to be about four times larger than the baseline, allowing for more than 3,000 square millimeters of active logic silicon per product. The
InFO package allows the chip to "fan-out" to add additional connections outside of the SoC's standard floor plan. This means that, although the chip logic area can be small, the chip is larger than the logic circuit to accommodate all the necessary pin-out connections. TSMC has offered InFO for many years, but with the support of 3DFabric, it will now offer different types of InFO related to in-package connectivity.
TMSC's packaging technology can also be combined in the same product. By implementing both front-end (SoIC) and back-end (InFO) packaging, new product categories can be created. The company made a model like this:
From the looks of it, TSMC will be offering customers more packaging options in the coming years. Their main competitor here appears to be Intel , which has been able to implement its EMIB and Foveros technology in some current products and some upcoming products. TSMC will benefit from working with more projects and customers.
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