TSMC held a shareholders' meeting today. According to DigiTimes, at the shareholders' meeting, TSMC Chairman Liu Deyin confirmed that TSMC has an N4 process node.
Today, when the process is becoming increasingly difficult to improve, TSMC has set up optimization nodes for itself to optimize the current mass production process to the greatest extent. For example, they set up an N6 process between N5 and N7, which is an optimized version of N7+, uses EUV, and will use more EUV layers than N7+. Because the more advanced the process, the more expensive it is, the N6 between N5 and N7 will provide some customers with an advanced process that is more acceptable.
The latest N4 node confirmed today is an optimization node between N3 and N5. It is based on N5 and is the third version of the optimization process of TSMC in the 5nm era. It is expected to enter the mass production stage in 2023. Like N6, it is compatible with N5, which can allow many chip companies to exchange for better processes at lower costs. It just so happens that today, there are rumors that TSMC will provide more variant processes in the 5nm era, besides N5P, and this is probably one of them.
In addition, according to AnandTech editor Dr. Ian Cutress, TSMC has collectively referred to the N5P process as N5.
Driven by the strong demand for mobile chips, TSMC can be said to be not short of money at all. They said yesterday that the N5 process has attracted many customers since 2019, including mobile communications and HPC, and the process will also be optimized for two different applications.
It is not known whether TSMC has other optimization processes based on N5. It is expected that TSMC N5 will become the next process with a very long service life after N7.
