Under the trend of continuous shrinking semiconductor transistor size and increasingly complex chip functions, testing has become a key link before the product is put into production. With the introduction of stricter Acceptable Quality Level (AQL) certification, testing methods are constantly innovating. Among them, system-level testing (SLT for short) is one of the important methods.
In fact, the system-level testing that is now highly concerned by engineers and can solve many test problems is not a technology that has only appeared now. At least in the field of computing, it has been in use since the late 1990s. Nowadays, as the number of transistors integrated into chips increases exponentially, the complexity of chips is also increasing. In this case, more IC manufacturers use SLT to improve the yield and quality level of chip systems. What is unique about
system-level testing?
What is SLT, why is it unique? What problems can be solved?
SLT is also called functional testing. It is a method to test the chip to be tested (DUT) in simulated terminal usage scenarios. By running the operating system and using the chip to be tested, there is no need to create a test vector like a traditional automatic testing device (ATE). SLT still needs to be written, but it is written in different ways.
So, what are the unique features and advantages of SLT?
In the past 20 years, the entire SLT market has grown considerably. The complexity of mobile processors in mobile phones and tablets, the increase in critical tasks, and time-to-market competition are the main reasons driving their growth. The reason why
SLT is becoming more common is that many trends in the chip industry are driving its popularity.
First of all, the quality requirements are increasing. In the past 10 years, people have relied more on electronic devices such as mobile phones. The high-quality requirements of chips have prompted manufacturers to conduct comprehensive testing of their chips and systems to reduce the possibility of end users encountering problems after purchasing products. To this end, SLT in the mobile field is entering a rapid growth model.
The trend in the automotive field is particularly obvious. In assisted autonomous vehicles, electronic devices or software are used to perceive events and react to events through automatic steering or braking. The mission-critical standards of ADAS ( Advanced Driver Assistance System ) require higher standards, which means that ultra-high power devices, mixed signal device performance, platform efficiency and thermal stability running in applications are crucial.
From a market competition perspective, chip suppliers are constantly pushing technology to the limit to improve performance, battery life and yield, which means they need to do the following:
- Delivery products of new process nodes as early as possible, although the process defect rate may be relatively high.
- runs at low voltage as much as possible to extend battery life.
- fine-tune PLL settings to maximize yield.
- adopts more cutting-edge packaging technology to improve transistor density and performance.
In addition, in the infotainment part of the car, automobile companies are closer to the forefront of technology than ever before. Using cutting-edge technology to achieve higher stability will help shorten the time to market for automotive infotainment products.
In the future, the next growth area of SLT is big data processing and edge/cloud AI (artificial intelligence) applications, which will likely surpass the computing field.
In view of the above requirements, it is necessary to pass a lot of testing to ensure that the finished product is used with high-quality components. As technology continues to push to its limits, the use of SLT helps prevent missed faults and ensures that components reach the required high quality levels. In addition, while improving product quality, operating equipment as close as possible to terminal applications can also help shorten product time to market.
Traditional test coverage has become more challenging
IC manufacturers are compressing more functions into a given chip, both self-developed and third-party designs. Under the trend of continuous shrinking semiconductor transistor size and increasingly complex chip functions, testing has become a key link before the product is put into production. With the introduction of stricter Acceptable Quality Level (AQL) certification, testing methods are constantly innovating. Among them, system-level testing (SLT for short) is one of the important methods. In fact, the system-level testing that is now highly concerned by engineers and can solve many test problems is not a technology that has only appeared now. At least in the field of computing, it has been in use since the late 1990s. Nowadays, as the number of transistors integrated into chips increases exponentially, the complexity of chips is also increasing. In this case, more IC manufacturers use SLT to improve the yield and quality level of chip systems. What is unique about system-level testing?
What is SLT, why is it unique? What problems can be solved?
SLT is also called functional testing. It is a method to test the chip to be tested (DUT) in simulated terminal usage scenarios. By running the operating system and using the chip to be tested, there is no need to create a test vector like a traditional automatic testing device (ATE). SLT still needs to be written, but it is written in different ways.
So, what are the unique features and advantages of SLT?
In the past 20 years, the entire SLT market has grown considerably. The complexity of mobile processors in mobile phones and tablets, the increase in critical tasks, and time-to-market competition are the main reasons driving their growth. The reason why
SLT is becoming more common is that many trends in the chip industry are driving its popularity.
First of all, the quality requirements are increasing. In the past 10 years, people have relied more on electronic devices such as mobile phones. The high-quality requirements of chips have prompted manufacturers to conduct comprehensive testing of their chips and systems to reduce the possibility of end users encountering problems after purchasing products. To this end, SLT in the mobile field is entering a rapid growth model.
The trend in the automotive field is particularly obvious. In assisted autonomous vehicles, electronic devices or software are used to perceive events and react to events through automatic steering or braking. The mission-critical standards of ADAS ( Advanced Driver Assistance System ) require higher standards, which means that ultra-high power devices, mixed signal device performance, platform efficiency and thermal stability running in applications are crucial.
From a market competition perspective, chip suppliers are constantly pushing technology to the limit to improve performance, battery life and yield, which means they need to do the following:
- Delivery products of new process nodes as early as possible, although the process defect rate may be relatively high.
- runs at low voltage as much as possible to extend battery life.
- fine-tune PLL settings to maximize yield.
- adopts more cutting-edge packaging technology to improve transistor density and performance.
In addition, in the infotainment part of the car, automobile companies are closer to the forefront of technology than ever before. Using cutting-edge technology to achieve higher stability will help shorten the time to market for automotive infotainment products.
In the future, the next growth area of SLT is big data processing and edge/cloud AI (artificial intelligence) applications, which will likely surpass the computing field.
In view of the above requirements, it is necessary to pass a lot of testing to ensure that the finished product is used with high-quality components. As technology continues to push to its limits, the use of SLT helps prevent missed faults and ensures that components reach the required high quality levels. In addition, while improving product quality, operating equipment as close as possible to terminal applications can also help shorten product time to market.
Traditional test coverage has become more challenging
IC manufacturers are compressing more functions into a given chip, both self-developed and third-party designs.Taking mobile processors as an example, there were almost no many functions in the early days and only supported calls. Today, its functions have covered graphics, image processing, advanced security, etc.; in the past communication was digital processing, but now it uses voice and biometric data processing, and even includes AI algorithms such as dedicated neural network , and AP needs to be integrated with high-speed memory.
In addition to mobile devices, the processor can do many important things, such as health functions, recording and storage, connecting and controlling, communicating with sensors around the car, ensuring security, and simplifying people's lives through machine learning artificial intelligence. Failures associated with interactions with these functional blocks can be particularly difficult to capture, especially when the test interfaces in them are in different languages.
All these new functions are compressed into an AP, which also causes the number of transistors to continue to grow and surpass Moore's Law . However, as the industry continues to innovate, the limits of Moore's Law that people predicted do not seem to have come yet.
Of course, the test challenge is more than just functionality. When we squeeze exponentially growing transistors into the IC, there are times when trade-offs that may lead to the beginning of erosion of the test coverage achieved by traditional methods. Practice over the past few years has proved that with the increase in the number of transistors, the number of tests is increasing. It is difficult to achieve ATE growth at the same exponential rate as the number of transistors.
Therefore, as complexity increases, the chance of defects is higher, and more testing is required to avoid the increasing defect rate. SLT can help us solve these problems.
How to run SLT?
SLT is a functional test of the product in a way that closely matches its end use, and its "system" part is implemented on a customized system-level test board.
SLT's test process includes:
The first is to perform specific operations, run common functions and target applications inherent in some systems (such as starting chips or loading the operating system), or run specific programs written by certain modules (such as performance evaluation programs), and verify that they all work as expected. The "system-level test board" used is similar to the "reference design" or evaluation board provided to customers.
The second is to determine whether the operation is successful and measure it based on the test results or the success/failure of the operation. For example, when verifying whether an internal process is successfully executed, it can be used to use whether the operating system can be started successfully, or to check a certain measured value (comparison of performance test results and threshold values) as the basis for judgment.
Most of the time, the systems in SLT are equipped with some onboard processors to perform the test process. Since system-on-chip (SoC) and system-on-package (SiP) chips are the main test objects of SLT, the test processor is usually part of the chip to be tested. If this is not the case, the peripheral testing system of the chip to be tested usually needs to be equipped with a suitable processor.
The SLTB circuit around the device under test can vary according to the needs; it can also quickly and easily display the fault escape reported by the final customer on the screen. And to achieve this on ATE, a lot of fault analysis has to be done, traced functional faults to the transistor level to see if they have the ability to capture it. On the other hand, SLT can take the exact use case of igniting a fault and quickly add this functional test to the SLT test, stopping bleeding almost immediately while returning and digging out the root cause of the fault escape.
However, since SLT is a functional test that simulates real terminal usage scenarios, rather than a structural test in ATE, the test time of SLT is usually much longer than that of traditional ATEs. Therefore, the concept of parallel testing efficiency becomes even more important to maintain the cost-effectiveness of SLT. The ATE test time is in 10 seconds, while the SLT is in minutes or 10 minutes. It is conceivable that to achieve the highest efficiency, one order of magnitude is needed to add to each system and measure the station.
Due to the long test time, SLT testing equipment has higher station density and lower station cost compared with traditional ATE testing.
In the final analysis, it is still cost
Why is SLT a good solution? In the final analysis, it is cost. In the overall SLT testing strategy, it is always a good idea to capture early to avoid downstream process costs. ATE wafer testing performed well in early process capture failures, including: transistor-level problems, sensitivity to changing frequency/voltage levels, compliance with basic design specifications, etc.
Some failures are generated during the encapsulation process, and the ATE final test will be run to filter these problems. However, there are still some failures that are so subtle and complex that because of a small DPPM level, it is impossible to pass the test acceptance process.
For high general quality level requirements, ATE cost usually increases with the increase in testing time. This increase is generally controllable and to some extent linear. But at very high complexity/transistor count, to provide the same level of quality, the ATE cost will eventually reach the inflection point of the curve and begin to grow exponentially.
This is mainly because it takes a lot of time to find these failures, and it also needs to be tested with peripheral devices, some of which are done on today's ATE, including some levels of parameter test and functional test. However, in some cases, the additional number of circuits and the length of the tests can cause the policy to crash. Interestingly, the SLT cost/test time does not increase with the complexity, as it just starts a running application. That said, it is not a very cost-effective way to capture transistor-level design parameter failures. ATE has been very good at catching these failures over the past 50 years of history.
Why are many of the faulty classes captured in ATE not captured in SLT? This is because, unlike ATE, SLT does not systematically test every transistor and its parameters, but only tests a subset of real-world applications within the device and view the functional results. And running every imaginable application to excite every transistor and cause failure is nearly impossible. The cost-effectiveness of
SLT lies in the discovery of a reasonable percentage of failures, which are caused by areas where ATE cannot test or stimulating the chip and its peripheral multiple IP modules simultaneously.
The cost of a single SLT system may be similar to or slightly higher than that of an ATE system, but the unifying ability (the number of devices tested at one time) is much higher, so the cost per device may be about 1/4 or less than that of an ATE.
Because there are so many chips in parallel to test, the SLT test cost of each chip is lower than that of ATE. It is also a good environment for running tests that are impossible to achieve on ATE using real-world chip application scenarios.
Combining ATE and SLT strategies is an ideal solution to maintain extremely high quality levels and lowest cost as complexity continues to grow exponentially and the number of mission-critical applications continues to grow.
Several aspects of cost can be seen from the following figures: to some extent, ATE cost is linearly related to complexity/transistor count; SLT is not a cost-effective way to capture "typical" ATE failures; SLT is very cost-effective in filtering out the last few difficult-to-discover failures at the end of the test process; therefore, for applications with very high-quality demands, adding SLT to an existing ATE test process is usually the most cost-effective overall testing strategy.
Why is Teradyne?
What needs to be pointed out is that when deploying SLT, you don’t always have to bet. Many companies adopt different ideas about whether to conduct SLT testing and test the percentage of their products with SLT. This is a behavior that takes into account multiple factors and balances costs, and the philosophy of each company/application is usually slightly different.
Teradyne's SLT tester is that it is truly concurrently tested, each chip is completely independent of its adjacent chip, which is a more efficient way to perform SLT with batch processing.
In addition, there is a dedicated technical team in Teradyne's storage testing business unit. For more than ten years, they have successfully designed and manufactured ultra-large-scale automated production platforms. As a global leader in semiconductor testing, Teradyne combines storage automation architecture and expertise with semiconductor testing knowledge to use its Titan platform to bring differentiated SLT automation and testing solutions to market, helping users solve testing challenges.
SLT is a supplementary test step and extension for ATE testing equipment to reach the market. Teradyne provides solutions that support the entire test lifecycle, helping to achieve maximum test coverage and highest quality with the best time.
Conclusion
SLT has existed for nearly 30 years and is mainly used in cutting-edge large-scale digital computing applications. It is an application scenario test on chips using dedicated peripherals on system-level test boards. It is used to capture the last 0.00xx% failure and achieve the lowest possible error escape rate. The growth of
SLT is due to the increasing demand for quality, the rapid growth of mission-critical electronic application scenarios, the rapid increase in complexity of chip devices, and the continuous shrinking of the time-to-market window, especially certain fault categories can only appear in real application scenarios.
Teradyne makes full use of the technology of semiconductor ATE business, provides SLT differentiated mass production asynchronous automation platform, serves the majority of mobile phone application processor customers, demonstrates the leading position in the market, and continues to advance to the automotive and HPC fields.
In the final analysis, it is still cost
Why is SLT a good solution? In the final analysis, it is cost. In the overall SLT testing strategy, it is always a good idea to capture early to avoid downstream process costs. ATE wafer testing performed well in early process capture failures, including: transistor-level problems, sensitivity to changing frequency/voltage levels, compliance with basic design specifications, etc.
Some failures are generated during the encapsulation process, and the ATE final test will be run to filter these problems. However, there are still some failures that are so subtle and complex that because of a small DPPM level, it is impossible to pass the test acceptance process.
For high general quality level requirements, ATE cost usually increases with the increase in testing time. This increase is generally controllable and to some extent linear. But at very high complexity/transistor count, to provide the same level of quality, the ATE cost will eventually reach the inflection point of the curve and begin to grow exponentially.
This is mainly because it takes a lot of time to find these failures, and it also needs to be tested with peripheral devices, some of which are done on today's ATE, including some levels of parameter test and functional test. However, in some cases, the additional number of circuits and the length of the tests can cause the policy to crash. Interestingly, the SLT cost/test time does not increase with the complexity, as it just starts a running application. That said, it is not a very cost-effective way to capture transistor-level design parameter failures. ATE has been very good at catching these failures over the past 50 years of history.
Why are many of the faulty classes captured in ATE not captured in SLT? This is because, unlike ATE, SLT does not systematically test every transistor and its parameters, but only tests a subset of real-world applications within the device and view the functional results. And running every imaginable application to excite every transistor and cause failure is nearly impossible. The cost-effectiveness of
SLT lies in the discovery of a reasonable percentage of failures, which are caused by areas where ATE cannot test or stimulating the chip and its peripheral multiple IP modules simultaneously.
The cost of a single SLT system may be similar to or slightly higher than that of an ATE system, but the unifying ability (the number of devices tested at one time) is much higher, so the cost per device may be about 1/4 or less than that of an ATE.
Because there are so many chips in parallel to test, the SLT test cost of each chip is lower than that of ATE. It is also a good environment for running tests that are impossible to achieve on ATE using real-world chip application scenarios.
Combining ATE and SLT strategies is an ideal solution to maintain extremely high quality levels and lowest cost as complexity continues to grow exponentially and the number of mission-critical applications continues to grow.
Several aspects of cost can be seen from the following figures: to some extent, ATE cost is linearly related to complexity/transistor count; SLT is not a cost-effective way to capture "typical" ATE failures; SLT is very cost-effective in filtering out the last few difficult-to-discover failures at the end of the test process; therefore, for applications with very high-quality demands, adding SLT to an existing ATE test process is usually the most cost-effective overall testing strategy.
Why is Teradyne?
What needs to be pointed out is that when deploying SLT, you don’t always have to bet. Many companies adopt different ideas about whether to conduct SLT testing and test the percentage of their products with SLT. This is a behavior that takes into account multiple factors and balances costs, and the philosophy of each company/application is usually slightly different.
Teradyne's SLT tester is that it is truly concurrently tested, each chip is completely independent of its adjacent chip, which is a more efficient way to perform SLT with batch processing.
In addition, there is a dedicated technical team in Teradyne's storage testing business unit. For more than ten years, they have successfully designed and manufactured ultra-large-scale automated production platforms. As a global leader in semiconductor testing, Teradyne combines storage automation architecture and expertise with semiconductor testing knowledge to use its Titan platform to bring differentiated SLT automation and testing solutions to market, helping users solve testing challenges.
SLT is a supplementary test step and extension for ATE testing equipment to reach the market. Teradyne provides solutions that support the entire test lifecycle, helping to achieve maximum test coverage and highest quality with the best time.
Conclusion
SLT has existed for nearly 30 years and is mainly used in cutting-edge large-scale digital computing applications. It is an application scenario test on chips using dedicated peripherals on system-level test boards. It is used to capture the last 0.00xx% failure and achieve the lowest possible error escape rate. The growth of
SLT is due to the increasing demand for quality, the rapid growth of mission-critical electronic application scenarios, the rapid increase in complexity of chip devices, and the continuous shrinking of the time-to-market window, especially certain fault categories can only appear in real application scenarios.
Teradyne makes full use of the technology of semiconductor ATE business, provides SLT differentiated mass production asynchronous automation platform, serves the majority of mobile phone application processor customers, demonstrates the leading position in the market, and continues to advance to the automotive and HPC fields.
