Editor: La Yan As I wish, so sleepy
[New Zhiyuan Introduction] Samsung 3nm chip is here! Announcement on paper, or actual production?
Yesterday, the world-famous semiconductor giant Samsung announced a big news.
chip based on 3 nanometer (nm) process is officially in mass production! In terms of paper parameters,
can be said to have achieved a qualitative leap - performance has increased by 30%, power consumption has dropped by 50%, and the area has also been reduced by 35%.
The three big names in the middle are not holding ordinary "plates", but 3-nanometer wafers that have just been taken off the production line of Samsung's Hwaseong Electronics Park.
looked at the other team members around him, and they were also smiling quite happily. And is not comparing scissor hands, but "3" which represents 3 nanometers.
Full performance, energy consumption plummets
Speaking of this 3-nanometer chip that has achieved mass production for the first time, we have to mention the MBCFET technology behind it.
MBCFE breaks through previous FinFET performance limitations by reducing supply voltage levels to improve power efficiency while also improving performance by increasing drive current capabilities.
Speaking of the application of nanosheet transistors and semiconductor chips , this is the first time for Samsung. The purpose is to achieve high-performance, low-power computing services. Eventually it can also be used on mobile processors.
Dr. Siyoung Choi, Samsung’s president and head of foundry business, said, “We have always been developing very fast. Samsung has always followed cutting-edge technologies and then found ways to put them into production applications. For example, the first High- K metal gate, FinFET, EUV, etc. "
"Now, we are the first to study MBCFET."
Samsung's exclusive technology uses nanosheets with wider channels, and uses narrower channels. Compared with the traditional GAA technology of nanowire , it not only improves performance, but also improves energy utilization.
Not only that, by applying 3-nanometer GAA technology, Samsung can also adjust the channel width of the nanosheets to optimize power consumption and performance to meet the different needs of various customers.
In addition, the design of 3nm GAA is very flexible and is simply tailor-made for Design Technology Co-Optimization (DTCO). We mainly look at the three dimensions of chip power consumption, performance and area (PPA, Power, Performance, Area) to quantify after the application of new technologies.
Compared with the 5-nanometer process, the first-generation 3-nanometer process reduced energy consumption by up to 45%, improved performance by 23%, and reduced the area by 16% compared with 5-nanometer.
The improvement of one generation alone is already visible to the naked eye.
Not to mention the second generation PPA - the power consumption is reduced by 50%, the performance is improved by 30%, and the area is reduced by 35%. It is infinitely better than the first generation. Is the yield rate of
okay? Is mass production reliable?
In the eyes of outsiders, a process capable of producing 3 nanometers may be unimaginable, but some analysts have expressed other opinions.
SK Kim from Daiwa Capital Markets said, "It does make sense that Samsung can do this. But it is far from enough. Mass production is only the first step. Before you can use it to produce mainstream chips, such as mobile phone CPU This way, you may not be able to earn much more."
This is actually well-founded.
html News came out in April that the yield rate of Samsung's GAA-based 3nm process was only between 10% and 20%, which was much lower than expected.
Samsung needs to spend more effort and cost to solve this problem.
html It was reported again in May that the 3nm yield problem had been solved, and it was only in early June that it was announced that it would enter experimental mass production.
However, with the lessons learned in April, many experts in the industry have put a small question mark on the true situation of Samsung's 3 nanometers.
According to reports, on June 22, the market once again reported that the mass production of Samsung’s 3-nanometer chips was postponed again, again due to yield issues.
Moreover, Samsung has made a lot of jokes before by manufacturing chips for other major manufacturers. The funniest thing about
may be that the Snapdragon 888, which was super popular at the time, was nicknamed "Big Fire Dragon".
(Picture: The real body of the big fire dragon)
When Qualcomm found Samsung to OEM this chip, they did not expect Samsung to be so capable. Although they were all 5nm processes at the time, the 5nm technologies of Samsung and TSMC were very different.
data shows that Samsung’s 5-nanometer transistor density is only 1.27 million transistors per square millimeter, while TSMC has reached 1.73 million. A difference of 46%.
It’s funny to say that the “Big Fire Dragon” was so hot when used that it burned the CPU to the point of soldering.
It can be seen that apart from anything else, Samsung always feels that it is not interesting in terms of chip production.
But no matter what, as far as the 3-nanometer process is concerned, technology is technology, and it should be advanced or advanced.
abandons FinFET and adopts GAA technology for the first time
Compared with the "FinFET" technology used in traditional chips, the "GAAFET" technology used by Samsung clearly has an advantage.
"FinFET" technology has been used on chips for nearly 10 years. It has helped the chip complete the leap from the 28nm process to the 5nm process.
In contrast, the channel of "GAAFET" is surrounded by the gate on four sides, and the channel current is smoother than that of "FinFET" wrapped on three sides. This design further improves the control of current, thereby optimizing the reduction of gate length. Not only does it consume less power, it also consumes less power and is faster.
Samsung believes that using nanowire channel design requires stacking more wire layers to increase the total channel width. This process is not only complex, but the cost may be greater than the benefits.
Therefore, Samsung designed a new form of GAA - MBCFET (Multi-Bridge-Channel FET, multi-bridge-channel field effect transistor), using multi-layer stacked nanosheets (Nanosheets) to replace the nanometers in "GAAFET" Nanowire.
"MBCFET" adopts a sheet structure with a larger width, while retaining all the advantages of "GAAFET" and minimizing complexity.
Nanosheet-based "MBCFET" is extremely customizable. The width of the nanosheet is a key indicator in defining power and performance characteristics. That is, the larger the width of the nanosheet, the higher its performance.
Therefore, transistor designs focused on low power consumption can use smaller nanosheets, while those requiring higher performance can use wider nanosheets.
Now let’s take a look at the progress of TSMC’s big brother at this time.
TSMC did not choose GAA architecture transistors in the 3-nanometer process technology, but still used "FinFET". By reusing previously mature and stable technology, this will bring better stability to TSMC's products and at the same time Better control costs and maximize benefits.
The most important thing is that such an operation can buy TSMC more time to optimize the GAA transistor architecture.
According to data released by TSMC at the "2022 TSMC Technology Forum", it still uses the 3nm process technology of FinFET transistor architecture. Compared with the previous generation 5nm process technology, the performance will be improved by 18%, and the power consumption will be improved by 18%. It can be reduced by 34% and the transistor density can be increased by 30%.
It can also be seen from the table that some technical indicators of TSMC's 2nm process: compared with the low-cost version of the 3nm process, under the same power consumption, the performance of TSMC's 2nm process will increase by 10~15%; and Under the same performance, the power consumption of TSMC's 2nm process will be reduced by 23~30%; the transistor density will only increase by 10%. The main reason for this improvement of
is that in terms of transistor architecture, TSMC N2 abandoned "FinFET" and adopted a new nanosheet transistor architecture, which is TSMC's version of "GAAFET".
Last year, Digitimes showed that the transistor density achieved by Samsung's 3nm process was approximately 170 MTr/mm² (millions of transistors per square millimeter); and TSMC had already pushed the transistor density to 173 MTr/mm² as early as the 5nm era.
In addition, Wikichip predicted in the middle of last year that the transistor density of TSMC's 3nm process can reach 291.21 MTr/mm², which looks similar in this table from Digitimes.
If Samsung’s 3nm process is really only 170 MTr/mm² as shown in the table, then the gap between this and TSMC will be clear at a glance!
In the end, we will wait and see how much "shock" TSMC's 3nm will bring!
Reference:
https://news.samsung.com/global/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture
