Intel is increasing competition pressure with AMD Xilinx and plans to start selling smaller FPGA for industrial, automotive, communications, consumer electronics, medical devices and other markets where energy efficiency is preferred over speed.
The Santa Clara, California-based company plans to expand its Agilex series FPGAs to provide new chips codenamed "Sun Dance Mesa" for Edge and embedded systems. According to the company, it will perform more than 60% higher per watt than AMD's Xilinx chips when launched to the market next year.
The lingering complex between Intel and AMD
Field programmable gate array (FPGA) is a dedicated chip that can be reconfigured at any time to suit specific workloads, or toward new industry standards for the future. This allows the chip to run these workloads more efficiently than the essentially more general standard CPU. FPGAs also have greater flexibility than ASIC, ASICs are chips customized for specific processing jobs.
In a briefing ahead of the innovation campaign, Intel revealed a new roadmap for the product line, which includes mid-range Agilex FPGAs for the edge and embedded markets, where it is necessary to process data locally to control system-level latency and save power consumption at the edge. The new chip will replace the cyclone, Aria and Stratix FPGA based on 20nm, 28nm and other aging process nodes.
While it has been working to stay competitive with Xilinx in recent years, executives at the U.S. chip maker have promised it is ready to be a stronger competitor to AMD, which acquired FPGA giant Xilinx for $49 billion earlier this year. All contents of the
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Intel is racing to regain its foothold and become an unquestionable leader in the field of chip manufacturing. Gelsinger has developed a positive roadmap in 2021, and it will release a new generation of process technologies every year from 2021 to 2025.
Poulin said one of his plans is to bring Intel's programmable chips closer to the forefront of state-of-the-art process technology in its revitalized foundry services business IFS.
They still have many products on traditional supply nodes, many of which are not made in Intel. In some cases there are five, ten, or even twenty years nodes, currently moving the entire product portfolio to Intel manufacturing,
He is keen to put Intel's programmable solutions in the priority channel, as FPGAs are playing a bigger role in the broad market from aerospace and defense to industrial and automotive to 5G network .
They are also widely used by cloud computing leaders such as Amazon , Google and Microsoft to run network, security, storage and even machine learning workloads in servers at faster speeds and lower power consumption.
To enter the booming data centers and other markets, Intel is actively investing in high-end products of its Agile X Series FPGAs, which encapsulate high-density programmable logic tightly woven into the structure.
The company launched its high-performance Stratix 10 FPGA based on its 14nm node in 2018 and launched its first F and I series in the Agilex series based on its 10nm process technology in 2019.
It further pushes the envelope with the Agilex M series based on Intel 7 nodes, what the company calls the enhanced 10nm "super Fin" transistor technology, and is packaged with High Bandwidth Memory (HBM). While Intel announced the M-series earlier this year, Intel plans to release the product range in 2023 or 2024.
high-end chips consist of small chips (or tile) connected together using Intel's 2.5D advanced packaging technology called EMIB. The central tile loaded with FPGA programmable logic is surrounded by I/O tile with Ethernet ports and SerDes or memory tile for PCIe and Computation High Speed Link (CXL) interfaces. While advanced packaging provides Intel with greater flexibility and performance, it is a costly and power-consuming approach.
Hard and Soft Logic
While Poulin also plans to upgrade its high-end, chip-based Agilex FPGA series as part of the roadmap, in the future, he is keen to be Xilinx's stronger competitor in high performance.
Intel said that while Sundance will use a small portion of programmable logic elements (LE) in the core of its high-end FPGA (about 50,000 ), it uses a more energy-efficient single-chip configuration .
According to the company, the programmable chip is based on the same Intel 7 process as its high-end, memory-intensive Agilex M-series FPGA, with performance per watt of 1.6 times higher than Xilinx's rival 16-nanometer Artix UltraScale+ SoC.
The new Agilex family inherits many of the most important architectural features of its previous Agilex devices, including the next-generation Intel's "HyperFlex" programmable logic technology. The HyperFlex architecture adds a large number of "hyperregisters" to facilitate pipelined data through the FPGA connection structure. These devices prevent ducts inside the chip from clogging, thereby increasing their throughput. The
Sundance series also uses a new hardcore processor system (HPS), which consists of a dual-core arm cortex A76 CPU and a dual-core cortex A55 CPU, with a clock frequency of up to 1.8 GHz. CPU cores can -coupled using Arm's DynamIQ technology, which fuses Cortex-A76 and Cortex-A55 into a larger cluster of application processors to help provide higher power and performance for FPGA-equipped edge devices.
These chips will also integrate an upgraded version of the Digital Signal Processing (DSP) module in their previous Agilex FPGAs to provide better AI computing capabilities, as well as areas such as image and video processing.
In addition, it integrates a hard IP core for time-sensitive networks (TSN) to reduce latency in industrial networks, as well as the MIPI D-PHY interface for video processing, and support for the PCIe Gen 4 protocol.
Most importantly, the new chip will be equipped with a hard memory controller for DDR4, LPDDR4, DDR5 and LPDDR5 memory. Ethernet, USB port; general purpose IO; cryptography engine; and 28 GB/s transceiver.
Mid-range range
In addition to Sundance FPGA, executives said Intel will also add the mid-range Agile D series to the programmable chip family, which will contain about 100,000 programmable logic gates based on Intel 7.
Intel says D-series FPGAs may target many communications, industrial and robotics markets that are the same as their Xeon D SoC, and the structural performance per watt will be twice as high as competitors’ 7nm FPGAs. The initial chip will be sampled in 2023 and mass shipments will begin in 2024.
The company plans to bring its Agilex series into the future, which shows that it continues to see FPGA as a vital part of its future. Intel said its Agile Series FPGA roadmap will be extended to 2025 and has done a lot of work behind the scenes to build a strong product portfolio.
