Before 1990, the reduction in gate length was almost completely linear, and the chip's performance was intuitively reflected from the name "Xnm". The length and width of of each generation of transistor are 0.7 times that of the previous generation (length 0.7* width 0.7=0.49), that is, the area of a single transistor is reduced to 0.5 times the original, confirming the description of the double density of transistors. For example, 180nm130nm90nm65nm45nm32nm22nm, where "X" refers to the length of the chip gate, that is, the distance from the source to the drain of the MOS transistor . As the number of advanced processes is smaller, the greater the density of the corresponding transistor, the lower the chip power consumption and the higher the performance.
process is no longer equal to the gate length
In the subsequent technological evolution, the process node reduction speed is accelerated, about 0.72 times, and is no longer completely linear. The field effect transistors gradually deviate from the original fixed structure. For example, the spatial structure transistor of FinFET appears, and the channel becomes a three-dimensional surround, and the channel length gradually cannot represent the highest accuracy of the process. 7nm, 5nm, and 3nm are no longer representatives of channel length. It is an equivalent length, just a number.
gate length is an important indicator of chip manufacturing process. The smaller the gate length, the faster the current flows between the source and drain; Fin Pitch is also an important parameter to measure the advanced process. During the FinFET transistor period, increasing the fin height and reducing the spacing between fin can effectively increase the driving current, thereby improving efficiency; other measurement indicators include metal spacing and logic units. The smaller the metal spacing, the smaller the capacitance effect that needs to be overcome; the lower the minimum unit height of the logic unit, it has more advantages in 3D stacking. The most intuitive measure of chip performance is logic transistor density. The larger the transistor density, the more transistors it can accommodate more transistors in the same space. The more transistors the more transistors the processing operation units in the chip and the stronger the processing capacity of the chip. The greater the transistor density, the closer the distance between the transistors, the smaller the loss of electrons during movement, and the greater the power consumption. Comparison of technical parameters of the three foundry giants By comparing these indicators, you can also take a look at the process differences between Intel , Samsung , and TSMC. (MTr/mm2 refers to the fact that there are millions of transistors per square millimeter of ) In the 10nm process, from the technical level, whether it is fin spacing, gate length, metal spacing, and logic unit height, Intel is the best among the three companies. Comparing the specific parameters, you can find that: Intel's gate spacing in the 10nm process is the technical level that TSMC and Samsung can only achieve at 7nm; its minimum metal spacing of 10nm is even comparable to the 5nm process of Samsung and TSMC; in comparison of logic transistor density, we can find that Intel has a greater advantage (see the figure below). (estimated value comes from digitimes) Under the 10nm process, Intel's logic transistor density is about 101 million units/mm2, while TSMC and Samsung are only half that of Intel. At 7nm, it is still less than Intel's 10nm. Even Intel's 10nm can be compared with Samsung's 5nm. However, there are some errors in the direct comparison of these numbers. On the one hand, there is a method of calculating transistor density; on the other hand, there are different cell sizes of each company. For example: Intel's 10nm process has three different types of logic unit libraries, namely HD (high density, short libraries short library), HP (high performance, mid-height libraries medium height library), and UHP (ultra-high performance, tall libraries high library). The shorter the cell library, the lower the power consumption and higher the density, but the lower the peak performance. The 100.8 MTr/mm² listed by Intel actually refers to the HD high-density library (unit height 272nm, 8 fins). The densities of the other two cell libraries are: HP (high performance) cell library density 80.61 MTr/mm² (unit height 340nm, 10 fins); UHP (ultra-high performance) cell library transistor density 67.18 MTr/mm² (unit height 408nm, 12 fins). As Philip Wong, vice president of research at TSMC, said on Hot Chips 31: Now "Xnm" only represents the iteration of technology, and it has no clear meaning just like the model. This is also the reason why Intel later used Intel's "new chip technology naming new regulations" to redefine the chip process process , such as Intel 7, Intel 4, Intel 3, Intel 20A, Intel 18A and other rules. The advanced process of the chip cannot be judged only by how many nanoprocesses are. As we all know, Intel has been stuck on the 10nm yield issue for a long time. Its 10nm node did not choose EUV, and chose to continue to use ArF DUV, and did not increase the density of transistors by 2 times according to Moore's Law, but took the risk by 2.7 times. These are important factors that 10nm is blocked. Intel's 10nm process also introduced the expensive material cobalt to replace copper. Cobalt as the lower interconnect layer can increase the electromigration performance by 1,000 times, and the interlayer through-hole resistance can also be reduced by half, greatly increasing the durability of the chip. At the same time, the hardness of cobalt also brings various problems. Intel's strong 10nm performance is not unreasonable. However, Intel's 7nm and 10nm are parallel to a certain extent. The 7nm process will be their first process using EUV lithography technology + FinFET, which can achieve the density of 180 million transistors per square millimeter. But 7nm has not yet been released. Some time ago, Intel CEO Kissinger said in an interview with US media: Engineers have discovered some defects in the 7nm process and are currently understanding these defects and have plans to solve the 7nm process problem. The process route directions of Samsung and TSMC have already changed significantly. On the one hand, in the 7nm era, Samsung was the first to use EUV (extreme ultraviolet) lithography in multiple stacks. And TSMC did not use 4 EUV lithography layers until N7+. On the other hand, Samsung's transistor structure at 3nm has evolved from FinFET to GAAFET, while TSMC has to wait until 2nm for GAAFET applications. In the process change battle, several chip giants were fighting hard. Different naming rules made the entire market fall into " process anxiety". However, the product will eventually enter the market, and the specific performance still needs market testing. In this battle, all parties are working hard to move forward in the process. In addition to the blind spots of naming rules, the power consumption problem behind it is also highlighting. The most representative issue of yield is the "5nm power consumption collective overturn" incident. includes Qualcomm Snapdragon 888 that uses Samsung 5nm foundry, HiSilicon Kirin 9000 and Apple A14 that uses TSMC 5nm foundry. Where does the power consumption problem come from? In order to improve the performance of the chip, it is necessary to increase the control ability of the electronic switch to the current on and off to speed up the switch. This means that the switch is going to pass a larger current at a smaller size. The smaller the size of the switch, the higher the requirements for the preparation process, which makes the switch have more leakage current when it is closed. The power consumption generated in this part is uncontrollable, and whether it generates power consumption will be directly determined by the stability of the process. That is to say, the stability of the process determines the amount of power consumption, and power consumption is also an important parameter of chip yield. A more mature process generally has a yield rate of more than 90%. The yield of Qualcomm Snapdragon 8 Gen 1 produced by Samsung is only about 35%. The yield of the Exynos 2200 produced on the same production line is even lower than this value, so Samsung has also quickly launched an investigation into the 5nm OEM yield. Then look at the yield of the 3nm process. The difficulty of 3nm yield has soared. TSMC has continuously corrected the 3nm process for this reason, and divided multiple versions such as N3, N3E and N3B, looking for the most suitable solution and meeting the needs of different customers, but there are still many problems with the 3nm process solution. According to the original plan, Apple A16 chips should be the first batch of products that use TSMC's 3nm process, but after several rounds of twists and turns, Apple can only use the 4nm process improved from the 5nm process. However, recently, TSMC announced: "The development of the 3-nanometer process is in line with expectations, with a high yield and will be mass-produced later in the fourth quarter." The yield still needs to be measured at that time. Samsung's first batch of 3nm chips have entered the stage of risk mass production, but the transistor density, power consumption and yield are not satisfactory, and the early products are just mining machine chips with relatively simple structures. yield reflects the direct profit . The higher the wafer yield, the more qualified chips produced on the same wafer . If the wafer price is fixed, the more qualified chips are the number of qualified chips, the higher the production of each wafer, and the lower the cost per chip. Then, of course, the higher the profit. Nowadays, whether it is TSMC, Samsung, Intel, IBM, they are chasing 2nm. I wonder if the yield issue behind it has been taken seriously in the pursuit of advanced technology. 11965, then director of the Research and Development Laboratory of Fairchild Semiconductor Company, wrote an observation and comment report for the magazine " Electronics ". In the report, Moore mentioned that engineers can continuously reduce the volume of transistors, and the number of transistors and resistors in the chip will double every 18 months. The performance and capacity of semiconductor will increase exponentially, and this growth trend will continue. His prediction is called "Moore's Law". Nowadays, the chip development roadmap is deviating from Moore's Law, and the competition for advanced processes has become more complicated, and the anxiety caused by chip processes is becoming more and more obvious. Enterprise time for EUV and GAA
"process anxiety" ignores the yield contradiction
Conclusion
