After the 2019 VLSI Symposium in Japan, TSMC held a small press conference. Introducing the latest process and packaging technology, the following are the details: N7 TSMC believes that their 7-nanometer node is currently the most advanced logic technology.

After the 2019 VLSI Symposium in Japan, TSMC held a small press conference. Introducing the latest process and packaging technology, the following are the details:

N7

TSMC believes that their 7-nanometer node (N7) is currently the most advanced logic technology. At the recent VSLI workshop, TSMC co-authored a paper on their 7nm node, for which we recently presented design rule details. Except for a few major customers, most TSMC customers are said to go directly from N16 to N7. The N10 node is considered a short-lived node and is mainly used for yield learning. When going from N16 to N7, N7 offers 3.3x gate density and about 35-40% speed increase or 65% lower power. A key highlight of the

N7 process is its defect density. TSMC said that learning from the N10 node, the N7 D0 reduction ramp is the fastest ever, leveling off to a level comparable to the previous node. As companies join , HPC, and , they begin reporting defect densities separately for mobile customers and HPC customers, with die sizes of 250 mm² and larger.

learned lessons from the N10 node. The reduction ramp speed of N7 D0 is the fastest ever, which is the same as the previous node. As the company moves into high-performance computing, they begin reporting defect densities separately for mobile customers and high-performance computing customers with die sizes of 250 mm2 and above.

TSMC's demand for its 7nm node has declined slightly sequentially over the past half year, by about 1% sequentially. The vast majority of revenue continues to come from their very mature 16nm node. However, there was a slight increase in wafer shipments in the second quarter, which is expected to occur in the second quarter. When comparing to longer trends, this is actually the lowest Q2 volume in 3 years. Nonetheless, they believe N7 will reach 25% of revenue for the full year.

TSMC found that in the first half of last year, the company’s demand for its 7-nanometer node dropped slightly month-on-month, by about 1%. The majority of revenue continues to come from their very mature 16nm node. However, wafer shipments increased slightly, which was the consensus estimate for the second quarter. Compared to the long-term trend, this was actually the lowest Q2 volume in 3 years. Nonetheless, they believe N7 will reach 25% of full-year revenue.

Technology nodes are shared according to revenue, WikiChip analysis

TSMC wafer shipments

N7P

TSMC has begun to launch an optimized version of the N7 process called N7 Performance Enhanced Edition (N7P). N7P should not be confused with N7+. N7P is an optimized DUV-based process that uses the same design rules and is fully IP compatible with N7. N7P introduces FEOL and MOL optimization, which is said to improve performance by 7% at constant power, or increase power consumption by 10% at constant speed.

N7+

TSMC’s N7+ is their first process technology to adopt EUV in several key layers. N7+ entered mass production last quarter (second quarter). TSMC says their production volumes are comparable to N7. Compared with the N7 process, the density of N7+ is increased by about 1.2 times. It is said that the performance of N7+ is improved by 10% at the same power, or the performance is reduced by 15% at the same power. On paper, the N7+ seems slightly better than the N7P. Keep in mind, though, that these improvements are only available with the new physics re-implementation and the new EUV mask .

N6

N6 is planned to use more EUV layers than N7+. It is both a design rule and compatible with N7's IP and is intended to be the primary migration path for most customers. N6 designs can again be improved or re-implemented on N6 with EUV masking and fidelity to take advantage of the Polymer Diffusion Edge (PODE) and Continuous Diffusion (CNOD) standard cell pedestal rules, which are said to provide an additional 18% density Improve. It's worth emphasizing that the N6 is unique in that it will actually enter risk production early next year and peak before the end of 2020. TSMC said: N6 is an improvement based on the lessons learned from N7+ and N5 EUV.

N5

TSMC’s 5nm process is the next “full node” after N7. N5 entered the risk trial production stage in the first quarter of this year, and this process is expected to accelerate in the first half of 2020.N5 uses EUV extensively on "multiple layers". TSMC has shown very high yields, and in terms of D0, they are on a similar trajectory to the N7 production process. N5 is planned as a long-term node and is expected to grow faster than N7 in terms of revenue.

Compared to N7, N5 provides 1.8 times the logic density. In terms of performance, N5’s equal-power performance is increased by 15% and power consumption is reduced by 30% under the same performance. Like the N7, the N5 will come in two flavors - mobile client and high-performance computing (HPC). HPC units offer additional options for up to 25% performance improvements compared to N7.

N5P

As with their 7nm process, TSMC will offer an optimized version of its N5 process called N5 Performance Plus (N5P). This process uses the same design rules and is fully IP compatible with N5. Through FEOL and MOL optimization, N5P improves performance by 7% compared to N5 at equal power, and reduces power consumption by 15% at equal performance. The timetable for N5P is a bit vague at the moment, but TSMC hints that mass production will be by the end of 2020 or early 2021.

N3

TSMC said their 3nm process is progressing smoothly. N3 is expected to launch around 2022. While TSMC has previously talked about GAA as a potential successor to FinFETs, both TSMC and Intel are proving that FinFETs, which are currently easier to manufacture, can scale sufficiently in performance. Another node. We currently believe that TSMC may continue to use FinFET for its N3, but will move to GAA in subsequent nodes.

Analysis of WikiChip

Next-Generation Packaging

As the complexity and cost of leading-edge nodes increase, the demand for chip-based solutions continues to grow. The main three reasons are splitting the die into smaller chips, leveraging older, mature modules and other parts of SoC nodes that don't necessarily scale well, and enabling higher systems with components like HBM integrated.

TSMC offers a number of technologies as part of its Wafer Level System Integration (WLSI) platform, which is designed to cover everything from low-idle mobile applications to high-performance computing. Their chip-wafer-substrate (CoWoS) package targets artificial intelligence, networking and high-performance computing applications, while its integrated fan-out (InFo) package targets networking and mobile applications.

The TSMC InFO package is their general fan-out wafer level packaging (FOWLP) solution and comes in many different flavors depending on the application. InFO uses dense RDL and fine pitch through-package vias (TSMC is also called via InFO vias or TIV). They are suitable for anything from high-performance mobile devices to networking and HPC applications.

Especially for 5G mobile platforms, TSMC has InFO POP (InFO_POP) for mobile applications, InFO Antenna-in-package (InFO_AiP) for RF front-end module (FEM) applications and RF front-end module (MUST) Multiple stacks (MUST). Baseband modem.

D-MiM for higher bandwidth

InFO_POP One of the earliest examples was the Apple A10 released in 2016 (previous processors had regular POP). However, even InFO_POP has the disadvantage of limited memory bandwidth due to controller and TIV tones. This problem is further exacerbated by upcoming 5G and AI edge/mobile applications that are inherently more memory bandwidth limited. To overcome this problem, TSMC announced 3D-MUST-in-MUST packaging technology (note that MUST stands for multi-stack). 3D-MiM integrates multiple vertically stacked memory chips through integrated fan-out (InFO) WLS integration using high-density RDL and fine-pitch TIVs. As you might imagine, the I/O must be exposed on one side of the chip, which is independently connected to the SoC, forming a wide I/O interface.

TSMC demonstrated SoC technology with 16 memory chips in a single package. The chip has a footprint of 15 mm x 15 mm and a height of only 0.55 mm.Compared to the flip chip POP package, the chip has twice the memory bandwidth at half the height.

TSMC touted many other advantages. Since there is no substrate and no bumps, the distance from the memory I/O to the SoC is much shorter, resulting in better electrical performance characteristics. Additionally, the thinner profile is said to provide better cooling performance.

By the way, 3D-MiM is not limited to a single SoC. In fact, TSMC talks about using multiple SoCs along with a large number of memory chips (e.g. 2 SoCs with 32 memory chips) in order to create HPC applications with high bandwidth and low power as an alternative to current 2.5D (e.g. HBM) technology. A key difference here is that the InFO memory chips each connect directly to the SoC without the need for an underlying logic chip.

InFO package antenna (InFO_AiP)

TSMC has developed the InFO antenna package (InFO_AiP) specifically for 5G millimeter wave system integration. What this package attempts to solve is the link or interconnect between the actual chip and the antenna, which results in severe transmission loss. TSMC achieves this with a socket-coupled patch implemented in the RDL and an embedded RF chip in the mold compound itself, which interconnects directly to the RDL without bumps.

Since the performance of the interconnect between the antenna and chip is a function of surface roughness and transition between chip and package, the InFO material and RDL uniformity allow for lower transmission losses. Compared to flip-chip AiP, TSMC claims it can deliver up to 15% better performance, 15% lower thermal resistance, and a 30% lower thermal resistance.

Networking and High Performance Computing

For high performance computing and networking applications, TSMC offers CoWoS and InFO on substrates and memories (_oS/_MS).

CoWoS can be expanded to 2 reticles with aggressive line/space of 0.4μm/0.4μm. This is a very mature technology with very high output and has been in mass production for more than five years. CoWoS has been widely used on GPUs, but can also be found in various network applications. TSMC said they have had more than 15 tapeouts so far.

Currently, CoWoS supports 6 HBM2 modules up to 1.5 TB/s. TSMC reports research into higher bandwidth solutions and larger silicon area beyond 3 reticles.

For web applications, TSMC offers InFO on a substrate that can achieve up to 1 reticle of integrated Si area, but with a slightly looser L/S pitch of 1.5μm/1.5μm. Current technology has a minimum I/O pitch of 40μm and a minimum C4 bump pitch of 130μm. Production of InFO_oS began to ramp up in the second quarter of 2018. They are currently working on achieving integration of more than two chips and 1.5x reticle size silicon area.

For AI applications and similar applications, TSMC’s InFO memory substrates are designed for integration with HBM. This technology currently has 2μm/2μm RDL L/S and is limited to a single reticle. In many ways, TSMC charges InFO_MS as a performance-cost-sensitive alternative to CoWoS.

InFO Ultra High Density Package (InFO_UHD)

Two key parameters driving performance and power are write density and bump pitch. This is the goal behind InFO ultra-high-density packaging, and TSMC has reportedly reported 500 lines/mm of 0.8/0.8μmL/S, with up to 10,000 lines/mm².

System on Chip (SoIC)

SoIC is TSMC’s next generation of “true” 3D packaging technology. SoIC is a chip-on-chip (CoW) stacking approach that allows the integration of a mix and match of many different KGDs and even stacked KGDs - varying in size and process node. It is both a face-to-face and a face-to-back technique. Because from the outside it looks like any other standard chip, you can actually combine SoIC with existing technologies like InFO, CoWoS or flip-chip in the same package. Like InFO_UHD, it currently has 10,000 pcs/mm² bonding, and with the launch of "SoIC+" they can eventually reach 1 million pcs/mm².