In the past, lithography machine is an important tool to continue 's mol's law . EUV lithography machines are a major technological change in the 7nm era, and EUV is a key tool to make chips break through 7nm and 5nm. But with the evolution of lithography machines, the update speed of lithography machines is slowing down. So are there other technologies that can continue Moore's Law before the emergence of next-generation lithography machines?
Recently, Samsung said it is planning to use back-side power supply network (BSPDN) technology in the 2nm foundry process. In fact, in addition to Samsung, Intel and TSMC have all been involved in this technology, and BSPDN is also regarded by the industry as one of the key technologies that can make chips break through 3nm. In addition to wafer foundry semiconductor equipment manufacturers, they have also made layouts for this technology. So, what is the back power supply technology? What will it play in Moore's Law? In addition to BSPDN technology, what other technologies will continue Moore's Law? What is the power supply process on the back of
?
Back-side power supply is to separate the power supply network from the signal metallization scheme in the logic IC, alleviating wiring congestion at the back end of the line and providing power performance advantages. BSPDN attempts to address the growing problem of power delivery in transistor scaling. The resistance problem is a basic problem in electrical engineering. Resistance is an attribute of the material's resistance to current strength. The resistance of materials like copper is never a limiting factor, but as the copper wire shrinks, the resistance begins to rise exponentially.
The heterogeneous 3D-SOC method implemented through system architecture redesign and 3D integration technology has proven to be an attractive method to improve system performance. Additional performance improvements can be achieved by utilizing the back of the bottom wafer for power transmission and/or signal routing. When the transistor size cannot become smaller, stacking upwards may be a new path to continue Moore's law. Continuous layers will cause voltage to decrease, which will cause a higher resistance. The transition solution currently adopted by the industry is new metal layers, such as cobalt. Cobalt helps these wires maintain enough charge to transfer signals and power to the transistors to work, but this relationship is reaching a fundamental limit. This hinders the ability to make smaller transistors to some extent.
The underlying layer in semiconductor is crucial to the overall design of the key layer (the actual transistor itself). But making these huge stacks on the front creates even bigger problems, and that’s where BSPDN comes into play. Splitting the signal and power layer is a trick to scale transistor size more than shrinking from the physical perspective of geometric features, so researchers are reorganizing the interior of the semiconductor structure, and removing the power signal and signal lines into just one signal line will make room for more transistors. BSPDN will do this by placing the signal layer on the top of the chip and placing the power layer on the bottom of the chip. Advantages and Challenges of
BSPDN
BSPDN concept was first proposed by IMEC in 2019. IMEC researchers Dragomir Milojevic, Geert Van der Plas, Eric Beyne and others conducted in-depth research and exploration of various promising methods to date. They introduced the advantages of 3D-SoC design and back interconnection in specific circuits in two papers published at the 2021 IEEE International Electronic Devices Conference.
Compared with FSPDN, BSPDN has a 44% performance improvement and a 30% power efficiency improvement. Use the "idle" back of these chips to route signals or directly power transistors in the 'logic wafer'. Traditionally, signal networks and power transmission are placed on the front of the wafer, and they compete for space in complex back-end (BEOL) interconnect solutions. In these designs, the back of silicon wafer is used only as a carrier.
In today's processors (left), both signal and power arrive from above to silicon (light gray). BSPDN will separate these functions, save power and make more space for signal paths (right), Source: IEEE Spectrum
imec Cooperating with UK Arm to conduct a quantitative evaluation of the back power supply method. In the past, lithography machine is an important tool to continue 's mol's law . EUV lithography machines are a major technological change in the 7nm era, and EUV is a key tool to make chips break through 7nm and 5nm. But with the evolution of lithography machines, the update speed of lithography machines is slowing down. So are there other technologies that can continue Moore's Law before the emergence of next-generation lithography machines? Recently, Samsung said it is planning to use back-side power supply network (BSPDN) technology in the 2nm foundry process. In fact, in addition to Samsung, Intel and TSMC have all been involved in this technology, and BSPDN is also regarded by the industry as one of the key technologies that can make chips break through 3nm. In addition to wafer foundry semiconductor equipment manufacturers, they have also made layouts for this technology. So, what is the back power supply technology? What will it play in Moore's Law? In addition to BSPDN technology, what other technologies will continue Moore's Law? What is the power supply process on the back of Back-side power supply is to separate the power supply network from the signal metallization scheme in the logic IC, alleviating wiring congestion at the back end of the line and providing power performance advantages. BSPDN attempts to address the growing problem of power delivery in transistor scaling. The resistance problem is a basic problem in electrical engineering. Resistance is an attribute of the material's resistance to current strength. The resistance of materials like copper is never a limiting factor, but as the copper wire shrinks, the resistance begins to rise exponentially. The heterogeneous 3D-SOC method implemented through system architecture redesign and 3D integration technology has proven to be an attractive method to improve system performance. Additional performance improvements can be achieved by utilizing the back of the bottom wafer for power transmission and/or signal routing. When the transistor size cannot become smaller, stacking upwards may be a new path to continue Moore's law. Continuous layers will cause voltage to decrease, which will cause a higher resistance. The transition solution currently adopted by the industry is new metal layers, such as cobalt. Cobalt helps these wires maintain enough charge to transfer signals and power to the transistors to work, but this relationship is reaching a fundamental limit. This hinders the ability to make smaller transistors to some extent. The underlying layer in semiconductor is crucial to the overall design of the key layer (the actual transistor itself). But making these huge stacks on the front creates even bigger problems, and that’s where BSPDN comes into play. Splitting the signal and power layer is a trick to scale transistor size more than shrinking from the physical perspective of geometric features, so researchers are reorganizing the interior of the semiconductor structure, and removing the power signal and signal lines into just one signal line will make room for more transistors. BSPDN will do this by placing the signal layer on the top of the chip and placing the power layer on the bottom of the chip. Advantages and Challenges of BSPDN concept was first proposed by IMEC in 2019. IMEC researchers Dragomir Milojevic, Geert Van der Plas, Eric Beyne and others conducted in-depth research and exploration of various promising methods to date. They introduced the advantages of 3D-SoC design and back interconnection in specific circuits in two papers published at the 2021 IEEE International Electronic Devices Conference. Compared with FSPDN, BSPDN has a 44% performance improvement and a 30% power efficiency improvement. Use the "idle" back of these chips to route signals or directly power transistors in the 'logic wafer'. Traditionally, signal networks and power transmission are placed on the front of the wafer, and they compete for space in complex back-end (BEOL) interconnect solutions. In these designs, the back of silicon wafer is used only as a carrier. In today's processors (left), both signal and power arrive from above to silicon (light gray). BSPDN will separate these functions, save power and make more space for signal paths (right), Source: IEEE Spectrum imec Cooperating with UK Arm to conduct a quantitative evaluation of the back power supply method.Arm demonstrated the beneficial effects of using BSPDN in CPU design through simulation experiments, which was made from a 3nm process developed by IMEC. In this design, the interconnect metal located on the back of the wafer is connected to the 3nm transistor on the front of the wafer through a through silicon hole (TSV) located on the embedded power rail (BPR). Arm researchers found that BPR itself could build a power network that is 40% more efficient than a normal front-end power supply network. imec collaborated with Cadence to evaluate and optimize some of the SRAM macro and logic circuit designs that are wired from the back. The results show that BSPDN is significantly more advantageous in improving the delay and power efficiency of long interconnect signal wiring compared to front wiring. For SRAM macros, up to 44% performance improvement and up to 30% power efficiency improvement. For logic units, BSPDN increases speed by 2.5 times and energy efficiency by 60%. Although the advantages of are obvious, BSPDN is still a certain distance away from being truly commercialized. The realization of a true back-powered network comes with additional technical complexity. A dedicated wafer thinning process is required and the ability to handle the nano-silicon through-hole (n-TSV) electrically connecting the back of the device wafer to the front. Intel and TSMC have announced that they will use BSPDN in the 2nm process. Intel and TSMC's competitive roadmap depends largely on the implementation of BSPDN, and it can be said that Intel's entire transformation depends on this technology. Intel calls its own BSPDN Power Via, and Intel will realize its own 2nm through Power Via technology and RibbonFET. This is a bold attempt by Pat Gelsinger and Intel for their architecture. For Intel, this may be an opportunity to regain the lead in advanced technology. Compared with Intel, TSMC is more conservative in the application of BSPDN technology. The BSPDN implementation method chosen by TSMC is a low-complexity embedded power rail, which has a relatively high success rate because it can be done on existing tools. If Intel loses its lead over TSMC because it cannot use EUV earlier, then TSMC may lose its lead in transistor density because it does not take active design measures to improve performance. With the addition of Samsung, all three foundries competing in advanced processes have joined the research of BSPDN, which also means that BSPDN may become a huge turning point. In addition to wafer manufacturing companies, their upstream equipment companies have also conducted research in the field of BSPDN. Applied Materials, a new Wafer to Wafer tool launched by Applied Materials in partnership with BESI, is a new Wafer to Wafer tool provided by Tokyo Electron. These markets are a huge incremental growth driver, with back-powered cabling equipment expected to grow at a three-fold growth rate now made by wafers. Advanced process has gone through a transition from plane to FinFET, to GAA and ultimately GAA with BSPDN. Intel, TSMC and Samsung's unanimous choices show that it is not enough to break through 2nm to innovate in transistor structure alone. Moore's Law will no longer rely entirely on the realization of transistor size scaling through lithography machines. So, can we use which link to make the chip more efficient in a smaller area? When the process enters 3nm, the scaling problem has begun to move towards verticality, and advanced packaging has begun to play an increasingly important role in this process. As a new technology, BSPDN is actually a continuous extension of the trend of advanced packaging. Traditionally we made semiconductors only on one side, but now we have started using hybrid bonding to bond the chips together. Engineers realized we could bond the power layer to the bottom of the chip, saving space and solving resistance problems. Whether it is to continue Moore's Law or surpass Moore's Law, it is inseparable from advanced packaging technology. Advanced packaging is expected to become an important leverage to leverage the semiconductor industry to continue to move forward. Traditional packaging technology usually refers to the process form of cutting the wafer into a single chip and then packaging it. It includes a double row of vertical packaging DIP and a ball array packaging BGA, which requires soldering lines.Advanced packaging includes packaging technologies such as flip-flop, bump, wafer-level packaging, 2.5D packaging, 3D packaging, etc., and its technology does not require the use of line welding. Advanced packaging has become a new focus for the three foundries of TSMC, Intel and Samsung. In terms of advanced packaging technology, TSMC has made efforts in the CoWoS and InFO series packaging technologies to achieve better performance, power, form factor and function system-level integration. Intel has advanced packaging technology fields, including EMIB and Foveros to help chip design companies integrate different computing engines and process technologies. At the Intel On Technology Innovation Summit held in September this year, Pat Kissinger introduced that Intel foundry services will usher in the "era of system-level foundry" and Intel will also provide packaging business. Samsung has launched the 2.5D packaging technology I-Cube and the 3D packaging technology X-Cube, which can stack different chips based on TSV silicon perforation technology. It has been used in 7nm and 5nm processes. High-NA will help resolve resolution errors, but for 2nm or more advanced nodes, the next stop will be more advanced packaging type innovations in the manufacturing process. This is another long-term technical test for semiconductor processes. The fate of the three largest fabs depends on advanced packaging strategies, not on lithography technology. When lithography machines become controllable variables, the choice of these packages is the next important factor that drives the chip process forward. The importance of advanced packaging means that the importance of back-end packaging companies is also increasing. This is also one of the most popular factors in design technology collaborative optimization (DTCO) becoming an industry hot. Changdian Technology means that to create competitive products, we must achieve industrial chain coordination, multi-scale collaborative design, multi-physics collaborative design, and design and process technology collaboration. This reflects a trend that continuation of Moore's law will require the joint efforts of participants at all levels. ?
BSPDN
Several major semiconductor manufacturers have started BSPDN research
breaks through 3nm, what other key technologies are there?
Advanced packaging has become a new focus for the three foundries of TSMC, Intel and Samsung. In terms of advanced packaging technology, TSMC has made efforts in the CoWoS and InFO series packaging technologies to achieve better performance, power, form factor and function system-level integration. Intel has advanced packaging technology fields, including EMIB and Foveros to help chip design companies integrate different computing engines and process technologies. At the Intel On Technology Innovation Summit held in September this year, Pat Kissinger introduced that Intel foundry services will usher in the "era of system-level foundry" and Intel will also provide packaging business. Samsung has launched the 2.5D packaging technology I-Cube and the 3D packaging technology X-Cube, which can stack different chips based on TSV silicon perforation technology. It has been used in 7nm and 5nm processes.
High-NA will help resolve resolution errors, but for 2nm or more advanced nodes, the next stop will be more advanced packaging type innovations in the manufacturing process. This is another long-term technical test for semiconductor processes. The fate of the three largest fabs depends on advanced packaging strategies, not on lithography technology. When lithography machines become controllable variables, the choice of these packages is the next important factor that drives the chip process forward.
The importance of advanced packaging means that the importance of back-end packaging companies is also increasing. This is also one of the most popular factors in design technology collaborative optimization (DTCO) becoming an industry hot. Changdian Technology means that to create competitive products, we must achieve industrial chain coordination, multi-scale collaborative design, multi-physics collaborative design, and design and process technology collaboration. This reflects a trend that continuation of Moore's law will require the joint efforts of participants at all levels.
