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TSMC is also sprinting for advanced manufacturing processes, and simultaneously increases investment in advanced packaging, and supports local equipment/material vendors such as Hongsu, Jingte, Wanrun and Wangsi, to build a complete ecosystem, becoming an important tool to bind orders from major customers such as Apple.
TSMC has announced that its capital expenditure will reach US$15 billion to US$16 billion this year, of which 10% will be used for advanced packaging, with a conversion amount of up to NT$48 billion; at the same time, in response to the expansion of Nanke's production capacity, it will build a new 3D packaging and testing production line in Nanke, and continue to expand the advanced packaging and testing scale in Longtan and Zhunan.
TSMC emphasized that after entering the fifth generation of mobile communications (5G) era, many high-speed computing and on-board chips require advanced processes below 5 nanometers. Even mobile devices integrate chips with powerful functions such as AI and medical diagnosis, and use advanced packaging technology to stack them with other different chips, allowing Moore's Law to extend.
In view of this, TSMC is gradually increasing investment in advanced packaging and testing, and at the same time cultivates a batch of local equipment/material factories to closely form an ecosystem of interest sharing, becoming a powerful tool for TSMC to defeat Samsung and take the lead in global wafer foundry.
First, look at your wire and packaging technology integration. According to TSMC, the company continues to upgrade wafer-level system integration technology (WLSI) in wire interconnect spacing density and system size, pushing system performance forward and surpassing Moore's Law. WLSI uses front-section three-dimensional (3D) integration, system integration chip (TSMC-SoIC) and back-section three-dimensional integration to develop innovative technologies, including integrated fan-out (InFO) and CoWoS technologies. TSMC has the most advanced process wafer/chips, as well as hybrid matching front and rear 3D systems integration, so customers can use TSMC's unique integrated services from wafer to packaging to create differentiated products.
Secondly, according to semiconductor industry, TSMC is an essential SOIC (system single chip) packaging technology that is necessary for new applications of the next generation of 5G, which can be regarded as an advanced packaging technology that TSMC continues to dominate wafer foundry. The advanced package of is a wafer-on-wafer bonding technology, and is also an extension of TSMC's launch of CoWoS. It is a 3D IC process technology that allows TSMC to directly produce 3D ICs for customers.
According to TSMC, system integration chips (TSMC-SoIC) are an innovative wafer-level packaging technology that integrates multiple chiplets into a system single chip with smaller area and thinner profile. Through this technology, 7-nanometer, 5-nanometer or even 3-nanometer advanced system single chips can be integrated with multi-layer and multi-function chips, which can achieve high-speed, high-bandwidth, low-power consumption, high-pitch density, and minimum space-consuming heterogeneous three-dimensional integrated circuits. Unlike traditional packaging technology, TSMC-SoIC uses a critical copper-to-copper bonding structure with silicon guide holes (TSVs) to achieve the most advanced 3D IC technology. Currently, TSMC-SoIC has completed the TSMC-SoIC process certification, developed the micron-level bonding pitch process, and obtained extremely high electrical yield and reliability data, demonstrating that TSMC is ready and has the ability to produce TSMC-SoIC for any potential customer.
It is understood that in addition to using silicon perforation (TSV) technology, SoIC technology can achieve a bonding structure without protrusions, and can integrate many adjacent chips of different properties. It also uses many unique materials jointly developed by TSMC and material manufacturers to integrate different chips to achieve the same volume and increase performance of more than multiple times, which is equivalent to the extension of Moore's Law.
Third, Si Interposer and CoWoS are also powerful tools for TSMC packaging.
In 2019, CoWoS demand continues to be strong due to the rapid growth of the high-performance computing (HPC) and artificial intelligence (AI) market. The unique requirements of this product category include integrating logic chips with the highest computing power with memory chips with the maximum capacity and bandwidth, which is exactly what CoWoS has to offer. To meet the increasing production demand, advanced late-stage fabs AP3 and AP5 work with the original CoWoS fab AP1 to provide the CoWoS production capacity required by customers.
In terms of technology, the fourth generation CoWoS further improves the overall package performance by expanding the size of the silicon interposer layer, with an interposer area of up to 1,700 square millimeters, and is large enough to accommodate a full-reticle-sized single chip and a stack of up to six three-dimensional (3D) high-bandwidth memory (HBM). The fifth-generation CoWoS under development has an intermediary area of up to 2,400 square millimeters, and new chip architectures are considered, such as chiplets, system integration chips, and the third-generation high-bandwidth memory (HBM3).
Fourth, the advanced fan-out and integrated fan-out (InFO) packaging technology naturally need not be mentioned.
In 2019, TSMC continued to lead the world's mass production of the fourth generation of integrated fan-out stacked packaging technology (InFO-PoP Gen-4) to support the application of mobile application processors and integrated fan-out and substrate packaging technology (InFO_oS) high-performance computing (HPC) grain segmentation. The fifth generation InFO-PoP and the second generation InFO_oS have also passed the certification, supporting mobile applications and high-performance computing applications respectively. Under the fifth generation InFO-PoP certification, this technology can have smaller package sizes, more pin counts and better power integrity.
Second Generation InFO_oS provides more grain segmentation integration into larger package sizes and higher bandwidths. Continuous development of multi-grain heterogeneity integration with finer pitch grain-to-grain interconnects has resulted in a new integrated fan-out technology without substrates, supporting consumer applications. The new generation of Integrated Passive Device (IPD) provides high-density capacitors and low-effective series inductance (ESL) for enhanced electrical performance and has been certified by InFO-PoP. AI and 5G mobile applications will benefit from enhanced InFO-PoP technology, and the new generation of IPD is expected to enter mass production starting in 2020.
Finally, let’s learn about TSMC’s advanced wire technology.
According to TSMC, in order to strengthen customers' competitiveness, TSMC provides advanced wire technology to improve chip efficiency through innovation in wire technology architecture and the development of new materials. The innovative power distribution network (PDN) solution is to reduce the high voltage drop and resistance capacitance delay in traditional practices and to use better wiring resources to improve line density. New materials include metal and dielectric materials, and develop strong low-dielectric materials and lower equivalent capacitance structures.
In addition to the development of metal barrier layers, TSMC has also developed monometal elements, bi- and ternary alloys. Advanced technology research transistor structure and materials innovation continues to improve the efficiency of advanced logic technology and reduce power consumption. TSMC has always been at the forefront of the industry in research on two-dimensional materials and nano-carbon tube transistors.
In 2019, TSMC presented the first demonstration of a gate tungsten disulfide p-channel field effect transistor growing over a 40-nanometer channel length on a silica/silicon substrate at the Symposium on VLSI Technology (VLSI). No two-dimensional material layer transfer is used, and this direct chemical vapor deposition technology is more suitable for mass production.
Taipei also successfully pioneered the use of low-temperature, low-cost and high-mobility rear-process nano-carbon tube transistors that are compatible with the back-process process, and are heterogeneously integrated on advanced 28-nanometer silicon logic circuits. TSMC continues to look for emerging high-density, non-volatile memory hardware accelerators that support artificial intelligence and high-performance computing. TSMC's advanced technology research is expected to pave the way for continuous density reduction, improved efficiency, and reduced power consumption, and provide advanced logic technology to support operational and high-efficiency computing applications.
At present, Samsung is also increasing its investment in advanced packaging, hoping to compete with TSMC.
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