A small chip has become the ultimate competition for technological confrontation between superpowers. Whoever can master the chip manufacturing technology will be able to gain more voice and initiative in the future wave of digital industry development. From a certain perspective, chips also determine the prospects of a country's future technological development. It is precisely because countries and major chip factories have shown a radical appearance in the chip field.
As the most basic building block of the chip, the number of transistor determines the performance and power consumption of a chip. The more advanced EUV lithography machine is actually to stuff more transistors into a chip the size of a thumb.
However, when the chip process reaches the commercial stage of 7nm and 5nm, for ASML, the accuracy of lithography machine has basically reached the physical limit, and it is more and more difficult to make transistors by improving the accuracy of lithography machine. To solve this problem, major fabs have improved the manufacturing process by modifying the transistor gate shape, and the size of gate is equivalent to the chip manufacturing process.
accuracy is not enough. The transistor technology is used to make up the structure of the
transistor consists of three parts, namely the source, gate, and drain. The current will flow from the source to the drain. The gate is equivalent to a switch or gate to control whether the current passes, and the gate is also the most important part of the transistor. The early method of controlling gate switches was an electric field, so it was also called a field effect transistor, which is what we abbreviated as FET. Just like a dam in a river, it can block the passage of current when it falls. This is the mainstream application technology of 20nm and mature process chips.
However, with the improvement of the manufacturing process, the gate in the FET transistor is so small that it is difficult to control the current switch. Later, major fabs began to use FinFET fin field effect transistors. As the name suggests, the transistor shape is very similar to fish fins. In this way, the contact area between the gate and the electronic channel is greatly increased, thereby better controlling the switching of the current. This is also the transistor technology used in the 7nm, 5nm or even 4nm process technology .
However, entering the 3nm era, FinFET transistor technology is also a bit unbearable, so Samsung 's 3nm uses GAA transistor technology, also known as full-surround gate technology, through a circle of gates, the problem of current switches in process processes of 3nm and below is solved.
It is worth noting that these technologies require high-precision EUV lithography machines to be used. For my country's wafer factory, if we want to build chips with more transistors and stronger performance, there is a very realistic problem before us, that is, EUV lithography machines cannot enter the mainland market.
my country has successfully developed a new transistor technology
How to greatly increase transistor density without an EUV lithography machine? Fudan University gave us a big surprise!
According to the official news from the School of Microelectronics of Fudan University, the team of Professor Zhou Peng of the school, Bao Wenzhong of the researcher Bao and Wan Jing, a researcher at the School of Information Science and Engineering, developed a heterogeneous CFET technology with excellent performance. The relevant results have been published in the journal Nature-Electronics, and this technology can bypass EUV lithography machines.
heterogeneous CFET technology, a wafer-level silicon-based two-dimensional complementary stacked transistor. This transistor technology can use mature back-end processes to integrate new two-dimensional materials on silicon-based chips, achieving the effect of double the device integration density under the same process process. That is to say, if the chips in the FinFET process consist of 10 billion transistors, the number of transistors contained in the chips made using CFET technology will reach 20 billion, thereby achieving a significant improvement in performance.
According to the School of Microelectronics of Fudan University, this silicon-based two-dimensional complementary stacked transistor uses mature back-end technology to integrate new two-dimensional materials on silicon-based chips, and uses the highly matching physical characteristics of the two to realize 4-inch large-scale three-dimensional heterogeneous integrated complementary field effect transistors. This method can realize wafer-level heterogeneous CFET technology.
Compared with traditional silicon-based materials, it can further improve the integrated density of chip transistors, thereby meeting the process needs of high-performance and high-density memory chips.
In the industry, CFET transistor technology is also called the "soldier" of GAA technology of 3nm process chips. If this technology is put into domestic chip production lines, 14nm process chips can meet the performance needs of all industries at this stage and get rid of their dependence on EUV lithography machines.
When competition among Chinese and Western technologies has become a normal state, the localization of chip technology has become a must-take the path at the moment, and the continuous advancement of Chinese companies in chip stacking technology, core particle technology, photonic chip , quantum chip , and even transistor technology, we believe that in the near future, no matter which model makes breakthroughs, the localization of domestic chips will take a big step forward!
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