Simply put, the researchers innovatively designed a wafer-level silicon-based two-dimensional complementary stacked transistor that can double the device integration density at the same process node, thereby achieving excellent electrical performance.

2025/09/2507:22:36 science 1895

December 11th news, according to the official news of the School of Microelectronics of Fudan University, the team of Professor Zhou Peng of the school, Bao Wenzhong of the researcher Bao and Wan Jing, a researcher at the School of Information Science and Engineering, bypassed the EUV process and developed heterogeneous CFET technology with excellent performance. Related results have been published in the journal Nature - Electronics.

Simply put, the researchers have innovatively designed a wafer-level silicon-based two-dimensional complementary stacked transistor that can double the device integration density at the same process node, thereby achieving excellent electrical performance.

Simply put, the researchers innovatively designed a wafer-level silicon-based two-dimensional complementary stacked transistor that can double the device integration density at the same process node, thereby achieving excellent electrical performance. - DayDayNews

▲ The concept of silicon-based two-dimensional stacked transistors, wafer-level manufacturing and device structure (Photo source: Fudan University official website)

official said that extreme ultraviolet lithography equipment is complex, and the three-dimensional stacked complementary transistor (CFET) that can greatly improve the integration density under existing technology nodes is highlighted. However, the process complexity of all-silicon CFETs is high and the performance deteriorates seriously in complex process environments.

According to reports, this silicon-based two-dimensional complementary stacked transistor uses mature back-end technology to integrate new two-dimensional materials on silicon-based chips, and uses the highly matching physical characteristics of the two to achieve a 4-inch large-scale three-dimensional heterogeneous integrated complementary field effect transistor.

This technology can realize wafer-level heterogeneous CFET technology. Compared with silicon materials, the single-atom layer thickness of the two-dimensional atomic crystal makes it superior short-channel control capabilities in small-sized devices. This technology will further improve the integration density of the chip and meet the development needs of high computing power processors, high-density memory and artificial intelligence applications.

Editor: Xin Zhixun-Linzi Source: School of Microelectronics, Fudan University,


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