TSMC process technology roadmap and expansion plan:
At the TSMC technology seminar, the company announced its process technology roadmap and future expansion plans. The advanced N3 and N2 processes have received the most attention, with the 3-nanometer process developing 5 nodes in the next 3 years.
The initial 3-nanometer node, called N3, is expected to begin high-volume manufacturing in the second half of this year and be delivered to customers from early next year. Compared with N5, N3 reduces power consumption by 25% to 30%, improves performance by 10% to 15%, and has a logic density that is 1.7 times that of the latter. It is mainly aimed at early adopters such as Apple and obtains cutting-edge node benefits such as performance, power, and area. come advantages. In the next few years, TSMC will also launch four N3 derivative manufacturing processes: N3E, N3P, N3S and N3X. The process window of
N3 is relatively narrow, and the yield may not be suitable for all applications. N3E will solve this problem. According to TSMC data, N3E consumes 34% less power than N5, improves performance by 18%, and has a logic density that is 1.6 times that of the latter. In comparison, N3E is slightly lower in logic density than the original N3, but its power consumption and performance are even better. High-volume manufacturing of N3E will begin in the middle of next year, and commercial chips manufactured using the N3E process node are expected to be available from the end of 2023 to early 2024. In addition to N3E, there is also a performance-enhanced version N3P, a density-enhanced version N3S, and an ultra-high-performance version N3X. Under the
N3 process, FinFlex technology can be used to precisely customize to achieve higher performance, higher density and lower power consumption: dual-gate single fin (2-1) FinFET can bring smaller chip size and lower In terms of power consumption, tri-gate dual-fin (3-2) transistors can maximize performance, while dual-gate dual-fin (2-2) FinFETs can achieve a relative balance.
TSMC also officially announced the N2 process node this time. It will use the nanosheet-based GAAFET architecture for the first time and is scheduled to be put into production in 2025. As a new platform, N2 will widely adopt EUV extreme ultraviolet lithography. The new gate-all-around transistor structure will greatly reduce leakage current, improve performance, and reduce power consumption: performance can be improved by 10% to 15% at the same power and number of transistors, or power consumption can be reduced by 25% to 30% at the same frequency and complexity. At the same time, the node density of N2 will be more than 1.1 times that of N3E.
AVX512 can speed up the PS3 emulator by 30%
AVX512 has long been widely criticized, including by Linus Torvalds, and is considered a foolish waste of transistors in home Core processors. Starting with the 12th generation Core, Intel finally removed AVX512. Now this "useless" instruction set is finding even more uses in home entertainment applications.
The developers of the PlayStation 3 emulator RPCS3 said that compared to AVX2, AVX512 can bring up to 30% performance improvement to the emulator. Unfortunately, Intel has decided to completely block AVX512 from the CPU to the BIOS level. If you need to use it on a 12th generation Core, you can only look for an old processor produced last year with a ring LOGO on the top cover (rather than the new square LOGO that represents heterogeneity), and use it with an old motherboard BIOS without upgrading.
The good news is that in the second half of this year, AMD will bring the ZEN4 architecture Ryzen 7000 processor that supports AVX512. I wonder if Intel will let AVX512 return on the 13th generation Core.
