Preface
This document mainly introduces the rich hardware interface resources of the Allwinner A40i development board, as well as some precautions in development and design. Quanzhi's A40i development board is the latest representative work from Chuanglong Technology. Its core board adopts a "100% domestic + industrial grade" design, with exquisite appearance and high playability. In the situation where domestic chips are gaining momentum Next, is it really the first choice for electricity users? Lets come look! Because the content of
is too long, it is divided into three articles: upper, middle and lower. This article is the middle one and covers in detail: Watchdog interface, CAMERA interface, AUDIO interface, MIPI display interface , RGB display interface, LVDS display interface, HDMI OUT interface, VGA display interface, CVBS OUT interface, TVIN interface, etc. All embedded enthusiasts are welcome to pay attention and check it out.
Chuanglong Technology TLA40i-EVM is a 4-core ARM Cortex-A7 high-performance and low-power domestic development board designed based on Allwinner Technology's A40i processor.
development board hardware resource diagram 1
development board hardware resource diagram
A40i processor's IO level standards are generally 1.8V and 3.3V, and the pull-up power supply generally does not exceed 3.3V. When the external signal level does not match the IO level, A level conversion chip or signal isolation chip needs to be added in the middle. ESD design needs to be considered for buttons or interfaces. When selecting ESD devices, attention should be paid to whether the junction capacitance is too large, otherwise signal communication may be affected.
design notes: The
TWI0 bus has been designed to pull up a 2K resistor to 3.3V inside the core board. The
Watchdog interface
evaluation baseboard leads to a 3pin 2.54mm pitch pin header (J1) as the Watchdog function configuration interface, and the Watchdog function can be enabled through jumper cap configuration. The Watchdog timeout duration can be controlled in software through G19/PB12/WD_SET0.
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CAMERA interface
J11 is the CAMERA0 camera interface, and J12 is the CAMERA1 camera interface. They all use 2x 12pin pin headers with a spacing of 2.54mm.
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AUDIO interface
CON15 is the LINE IN audio interface, CON26 is the H/P (Headphone) OUT audio interface, both use 3.5mm audio sockets.
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CON28 is a MIPI display interface, using a 40pin FFC connector with a pitch of 0.5mm.
J7 is a capacitive touch interface for MIPI display, using 6pin FFC connector with a pitch of 0.5mm.
Figure 51
Figure 52
Design Notes:
(1) If the nINT pin of J7 needs to be allocated to use other IO, please use an IO pin whose pin signal name contains the EINTx field (supports interrupt function). The
RGB display interface
CON11 is an RGB display interface, using a 40pin FFC connector with a pitch of 0.5mm.
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Figure 54
Design considerations: The LCD0 signal used by the
RGB display interface has a multiplexing relationship with the LVDS0 and LVDS1 signals, as shown in the figure below.
Figure 55
outputs PWM to control the LCD backlight through the F24/PB20/PWM4 pin, and the external pull-down 4.7K resistor is reserved to ground. The
RGB display interface and LVDS display interface are connected to the TPX1, TPX2, TPY1, and TPY2 four-wire resistive touch signals at the same time. Please do not connect two display devices at the same time.
LVDS display interface
CON12 is a dual-channel 8bit LVDS display interface, using 2x 15pin double row pins with a pitch of 2.0mm, including LVDS signals and power supply. CON13 is a backlight control interface, using a 6-pin white terminal block with a pitch of 2.54mm. J5 is a resistive touch screen interface, using 4pin headers with a spacing of 2.54mm.
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Figure 57
Design considerations:
LVDS0, LVDS1 signals and LCD0 signals are in a multiplexing relationship. The
LVDS display interface and RGB display interface are connected to the TPX1, TPX2, TPY1, and TPY2 four-wire resistive touch signals at the same time. Please do not connect two display devices at the same time.
HDMI OUT interface
CON10 is HDMI OUT video output interface, using a standard 19pin HDMI socket.
Figure 58
Figure 59
Design Notes: The HPLG signal of the
HDMI socket needs to be pulled down with a 27K resistor to the ground. When the external device is connected, this signal will be pulled high. The IO level of
V9/HDMI_HSCL and W9/HDMI_HSDA is 3.3V, which needs to be converted to 5V level and then led to the HDMI socket.
VGA display interface
CON14 is a VGA video output interface, led by TVOUT0, TVOUT1, TVOUT2, using 15pin VGA socket .
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Design notes:
(1) The IO level of U5/PD26/LCD0_HSYNC and U6/PD27/LCD0_VSYNC is 3.3V, which needs to be converted to 5V level and then led to the VGA socket. The
CVBS OUT interface
J9 is the CVBS OUT interface, which is led out by TVOUT3 and uses RCA lotus base .
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TVIN interface
J8 is the TVIN interface, which is led out by TVIN0, TVIN1, TVIN2, TVIN3, and adopts the form of 6pin 2.54mm white terminal for .
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Figure 65
The second part of this article has been completed. The third part will explain the USB interface, Ethernet interface, 4G module expansion interface, WIFI module , Bluetooth module , SATA interface , SDIO of the A40i development board. interface, expand IO signal interface, etc. Through the detailed introduction of the hardware resources of the A40i development board, I believe that everyone is still very interested in this domestic board . It is also very suitable for application in the field of smart power. There are also many characteristic cases related to display, which you can learn about. .
