Preface
This document mainly introduces the rich hardware interface resources of the Allwinner A40i development board, as well as some precautions in development and design. Quanzhi's A40i development board is the latest representative work from Chuanglong Technology. Its core board adopts a "100% domestic + industrial grade" design, with exquisite appearance and high playability. In the situation where domestic chips are gaining momentum Next, is it really the first choice for electricity users? Lets come look! Because the content of
is too long, it is divided into three articles: upper, middle and lower. This article is the upper one and covers in detail: power interface, LED, BOOT SET startup selection DIP switch , KEY, serial port , CAN interface , Micro SD interface, SPI FLASH, RTC socket, etc. All embedded enthusiasts are welcome to pay attention and check it out.
Chuanglong Technology TLA40i-EVM is a 4-core ARM Cortex-A7 high-performance and low-power domestic development board designed based on Allwinner Technology's A40i processor. The core frequency is up to 1.2GHz. The A40i development board has rich interface resources. leads to dual network ports, dual CAN, dual USB, dual RS485 and other communication interfaces , onboard Bluetooth, WIFI, 4G (optional) modules, and leads to MIPI LCD, LVDS LCD, TFT LCD, HDMI OUT, CVBS OUT, CAMERA, LINE IN, H/P OUT and other audio and video multimedia interfaces, support dual-screen differential display, 1080P@45fps H.264 video hardware encoding, 1080P@60fps H.264 video hardware decoding , and support SATA mass storage interface.
Figure 1 Illustration of development board hardware resources 1
Figure 2 Illustration of development board hardware resources
The IO level standards of the A40i processor are generally 1.8V and 3.3V, and the pull-up power supply generally does not exceed 3.3V. When the external signal level and IO level When there is a mismatch, a level conversion chip or signal isolation chip needs to be added in the middle. ESD design needs to be considered for buttons or interfaces. When selecting ESD devices, attention should be paid to whether the junction capacitance is too large, otherwise signal communication may be affected.
Allwinner A40i core board
Allwinner A40i core board has onboard CPU, ROM, RAM, crystal oscillator , power supply, LED and other hardware resources, and leads to IO through stamp hole connection. For core board hardware resources, pin descriptions, electrical characteristics, mechanical dimensions, baseboard design considerations and other details, please refer to Chuanglong Technology's "SOM-TLA40i Core Board Hardware Manual".
Figure 3 Core board hardware block diagram
Figure 4
Figure 5
The power interface
CON1 uses a 12V DC input DC-005 power interface, which can be connected to a power plug with an outer diameter of 5.5mm and an inner diameter of 2.1mm. The power input has overcurrent and overvoltage protection functions.
SW1 is the power toggle switch.
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Design considerations:
- VDD_12V_MAIN outputs VDD_5V_SOM through WD1304E30-6/TR (DC-DC step-down chip) for use by the core board, and through another WD1304E30-6/TR The chip outputs VDD_5V_MAIN for use by the evaluation baseboard peripherals; at the same time, VDD_5V_MAIN outputs VDD_3V3_MAIN through 1 WD1304E30-6/TR chip for use by the evaluation baseboard peripherals.
- In order to make VDD_5V_MAIN and VDD_3V3_MAIN meet the system power-on and power-down timing requirements, the core board output R24/AP-RESETn needs to be used to control the power enable of VDD_5V_MAIN, so that the evaluation base VDD_5V_MAIN and VDD_3V3_MAIN power supplies are powered on later than the core board power supply.
- VDD_5V_MAIN does not reserve a large energy storage capacitor for the total power input inside the core board. When designing the baseboard, please place a large energy storage capacitor close to the stamp hole pad.
- VDD_3V3_LDO provides power for the evaluation backplane hardware Watchdog function circuit.
LED
evaluation baseboard has 6 LEDs on board. LED0 is the 3.3V power indicator light , which lights up by default after power-on; LED1 and LED2 are user-programmable indicators, controlled by GPIO, and light up by default at high level; LED3 is the 4G module status indicator light; LED5 and LED6 are Bluetooth Module status indicator.
Figure 13 Power indicator light
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Figure 15 User programmable indicator light
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Figure 17 4G module status indicator light
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Figure 19 Bluetooth module status indicator
Figure 20
BOOT SET startup selection DIP switch
SW2 is 1bit startup mode Select the DIP switch to support Micro SD, SPI NOR FLASH, eMMC, NAND FLASH and USB boot.
When BOOT SET is 0 (confirmed according to the evaluation baseboard silk screen), CPU will detect the storage device and start the system in the order of Micro SD - SPI NOR - eMMC - NAND.
- 0: Micro SD - SPI NOR - eMMC - NAND.
- 1: USB0.
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design notes:
- core board internal L7/FEL has been designed with a 10K pull-up resistor. When L7/FEL is high level (that is, SW2 is 0), the CPU will detect the corresponding device in sequence and start the system.
- Please refer to the evaluation baseboard BOOT SET circuit for boot configuration circuit design.
KEY
evaluation baseboard includes 1 system reset button CPU RESET (KEY1), 1 PMIC power on/off button PMIC PWRON (KEY2), and 3 user input buttons USER KEY0 (KEY3), USER KEY1 (KEY4), and USER KEY2 (KEY5).
Figure 23
Figure 24
Design Notes:
R24/AP-RESETn is the reset input pin of the CPU and is directly connected to the PWROK output pin of the PMIC. Since PWROK is set high after the PMIC is powered on, and R24/AP-RESETn controls the evaluation backplane power supply, a reset delay needs to be added to control the backplane peripheral reset. By default, please leave it floating to avoid affecting the power-on sequence.
Figure 25
PMIC_PWRON controls the pin for the switch of PMIC. Pressing and holding PMIC will shut down. Long press again and the PMIC will switch to power on. The PMIC has a 100K resistor internally pulled up, please leave it unconnected by default. The input range of
KEYADC0 and KEYADC1 is 0~2V. The 100K resistor has been pulled up to 3V inside the core board. The base board can control the input voltage between 0~2V through the voltage dividing resistor . The
serial port
evaluation baseboard has 6 serial ports onboard. CON2 is the USB TO UART0 serial port, CON5 is the RS232 UART3 serial port, CON6 and CON7 are the RS485 UART4 and RS485 UART5 serial ports respectively, and CON25 and CON27 are the TTL UART6 and TTL UART7 serial ports respectively.
USB TO UART0 serial port The
development board converts UART0 into a Micro USB interface through the CH340T chip, which is used as a system debugging serial port.
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RS232 UART3 serial port
development board converts UART3 to RS232 serial port through the UM3232EEUE serial port level conversion chip, using a 9-pin DB9 interface.
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RS485 UART4/RS485 UART5 serial port
development board uses two isolation transceivers CA-IS3082WX to convert UART4 and UART5 into RS485 serial ports respectively, using 3pin 3.81mm green terminals to lead out.
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UART6/UART7 serial port The
development board directly leads to UART6 and UART7 as TTL serial ports, and the interfaces use 4pin 2.54mm white terminals.
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CAN interface
CON9 (CAN0) and CON8 (CAN1) are 2-way CAN interfaces expanded through the SPI2 bus (2 chip selects), both using 3pin 3.81mm green terminals.
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Design Notes:
(1) If the nINT pins of U21 and U23 need to be allocated to use other IOs, please use IO pins whose pin signal names contain the EINTx field (supports interrupt function).
Micro SD interface
CON4 is a Micro SD card interface, which is led out through the SDC0 bus and adopts 4bit data line mode.
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design notes:
needs to connect SHIELD[1:4] of the TF seat shell to the digital ground.
SPI FLASH
evaluation baseboard carries a SPI FLASH (U6) chip with a capacity of MByte, using the SPI0 bus, and the chip select signal is CS0.
Figure 39
Figure 40
Design Notes: The SPI0 bus (PC0, PC1, PC2, PC23) used by
SPI FLASH belongs to the PC group IO, and the default power supply configuration of this group is 1.8V. The evaluation baseboard converts the SPI0 bus to 3.3V through the U77 chip and then connects it to the SPI FLASH, so the SPI0 bus transmission rate will be limited.
Note: can use a wide-voltage SPI FLASH chip to directly connect to the SPI0 bus (without going through U77), thereby increasing the SPI0 bus transmission rate.
Figure 41
RTC seat
evaluation baseboard uses the DS1307ZM/TR chip to implement the external RTC function. CON3 is an RTC button battery holder, suitable for button batteries ML2032 (3V rechargeable) and CR2032 (3V non-rechargeable). When using rechargeable batteries, plug the jumper cap into the J13 interface to charge. When using non-rechargeable batteries, do not insert the jumper cap into the J13 interface.
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The first part of this article has been completed. The second article will explain the Watchdog interface, CAMERA interface, AUDIO interface, MIPI display interface , RGB display interface, LVDS display interface, HDMI OUT interface, VGA display interface, CVBS OUT interface, TVIN interface, etc. Through the detailed introduction of the hardware resources of the A40i development board, I believe that everyone is still very interested in this domestic board . It is also very suitable for application in the field of smart power. There are also many characteristic cases related to display, which you can learn about. .
