Recently, Hunan University’s School of Semiconductor (School of Integrated Circuits) and the School of Physics and Microelectronics Sciences cooperated to use the Van der Waals integration strategy and combined with the physical properties of atomic-scale two-dimensional hafnium sulfide, it has obtained an ultra-thin hafnium oxide dielectric layer and an absolutely ideal gate dielectric/semiconductor interface, breaking through the bottleneck of the integration of ultra-thin dielectric layer of two-dimensional electronic devices and is expected to promote the development of two-dimensional integrated circuit . The result was published in the top international electronics journal Nature Electronics under the title "Molybdenum discardide transists with enlarged van der Waals gaps at their dielectric interface via oxygen accumulation".
2D semiconductors have chemically inert surfaces and usually lack hanging bonds and hydrophilic group , which makes the heterogeneous integration of ultra-thin dielectric materials face great challenges. At the same time, in order to maintain the low transistor preparation temperature, the gate dielectric material is mostly amorphous, which leads to a high dielectric/channel interface defective state density and a large transistor hysteresis voltage. Therefore, finding new technical solutions to optimize the interface between two-dimensional semiconductors and gate dielectrics, and achieving high-quality gate interfaces without damaging the channel's intrinsic performance is crucial to the construction of the new semiconductor device . Structural characterization and basic performance of
device.
When the distance exceeds 3 Angstroms, the coupling effect between the two materials will greatly weaken and form an interface close to physical adsorption. At this time, the electronic properties of the two materials no longer affect each other, and the coupling effect between the dielectric defect and the channel layer will be greatly weakened, and the respective inherent electrical characteristics will be retained. Through van der Waals heterogeneous integration, a van der Waals gap with a width of 5.3 angstroms was cleverly constructed between the gate insulating layer and the MoS2 channel (Figure 1), effectively opening the distance between the semiconductor channel layer and the gate insulating layer, realizing a heterogeneous interface of quasi-physical adsorption, removing the defect between the gate defect and the channel, and obtaining a MoS2 top gate transistor with a hysteresis voltage as low as 10 mV and a sub-threshold swing approaching the theoretical limit. Based on the excellent electrical performance of the transistor, an OR, AND, and non-logic gate circuit is assembled and ultra-high voltage gain is achieved.
Professor Liu Xingqiang and Professor Liao Lei, postdoctoral fellow Qin Wenjing and Wuhan University Professor He Jun are the co-corresponding authors of this work, and Hunan University is the first communication unit. Master's student Luo Pengfei and PhD student Liu Chang are the co-first authors of the article. This work has been supported by projects such as the Ministry of Science and Technology’s key R&D plan, National Natural Science Foundation of and Hunan Provincial Natural Science Foundation.
Source | Semiconductor College (Integrated Circuits College)
Correspondent | Liu Chang
Intern Editor | Li Hao
Editor in charge | Qin Wenzeng Tang Si
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