core stuff (public number: aichip001) Author | ZeR0 Edit | Moying
chip news on March 3, Intel, TSMC, Samsung, the world's three major chip manufacturers, including Intel, TSMC, and Samsung, Sun and Moonlight, as well as top chip design companies in the x86 and Arm ecosystems, AMD, Arm, Qualcomm, Google Cloud, Microsoft, Meta and other technology giants have joined forces to launch a new general-purpose chip interconnection standard - UCIe!
This standard was designed for chiplets (also known as chip grains and chiplets). It hopes to build an open chiplet ecosystem for packaging innovation, which not only simplifies the process of all related links, but also provides chip products across chip manufacturers and process nodes, making interoperability and mixing between chiplets of different manufacturers possible.
1. Developing chiplet interconnection standards is the general trend
Now, after years of hardship, this technology has finally ushered in a milestone - Intel, AMD, Arm, Sun and Moonlight, Google Cloud, Microsoft, Meta, Qualcomm, Samsung, and TSMC have joined forces to create a new open chip interconnection standard, UCIe, and the UCIe 1.0 specification has been released.
It is worth noting that Nvidia has not appeared on the member list of this alliance, and we have not seen RISC-V yet.
UCIe website: https://www.uciexpress.org
1. Developing chiplet interconnection standards is the general trend
In the context of Moore's law, chip manufacturers are working hard to cope with increasingly difficult scale problems. By reducing costs and using different types of process nodes in a single package, chiplets that can shorten the overall chip development and production process and reduce costs are gradually becoming mainstream.
With the help of chiplet technology, a large chip does not need to use expensive advanced processes such as 7nm and 5nm. Instead, it can mix and match chip modules made by multiple chip manufacturers and multiple process nodes according to its own needs and package them together. This not only helps improve efficiency but also reduces the economic burden.
's pursuit of performance and efficiency also drives people to develop a continuous interest in chiplets. PCIe is slow by chip standards, has high latency, and has high energy consumption for data transmission, so chip manufacturers want to integrate more functions into the chip to reduce latency and power consumption.
If implemented with chiplet, this may increase performance by more than 20 times, or reduce power consumption to 1/20 of the original.
However, there is a lack of standardized connections between chiplets, and there are a large number of customized proprietary interconnects on the market, which is difficult to achieve with other designs. In addition, the long-term lack of standardized validation and verification of chip design and interconnection has made it impossible for the chip ecosystem to achieve.
This is what the UCIe alliance wants to do - implement standardized connections between chiplets such as core, memory and I/O.
2. Layered protocol, supporting 2D and 2.5D encapsulation
UCIe is a hierarchical protocol, including physical layer, Die-to-Die adapter and protocol layer.
As shown in the figure above, the physical layer can be composed of all types of current packaging options from multiple companies, including 2D packaging, 2.5D packaging, such as Intel EMIB, TSMC CoWoS, Sun and Moonlight FoCoS-B, etc. The standard will also be extended to 3D package interconnect in the future.
in the physical layer, its initial specification lists the electronic signal standards, number of lane, bump pitch (connection density) and channel length that the chip will use to communicate with each other. As long as one chiplet meets the standards, it can communicate with another UCIe chip.The
UCIe 1.0 specification has two performance/complexity standard levels.
"Standard Package" level specification is designed for low bandwidth devices using traditional organic substrates. These components will use up to 16 lanes, 100μm+ bump spacing, and extended channel lengths. It's like connecting two devices on a contemporary PCIe link, but putting them very, very close.
"Advanced Packaging" level specification covers all high-density silicon bridge-based technologies such as EMIB and InFO, requiring smaller bump spacing in the range of 25μm~55μm. Due to the greater density, each cluster requires 4 times the lane and the channel length is less than 2mm. Promoters of
UCIe believe that if the current 45μm bump spacing technology is adopted, the advanced packaging device will be able to provide shoreline (linear) bandwidth up to 1.3TB/s/mm. That is, 1.3TB of data per second can pass through the chip edge of 1mm.
The most performing devices usually stuff as much low-latency bandwidth as possible into the smallest area, but most designs do not require this level of performance, so designers can use a variety of means to customize the design. Therefore, the “Key metrics targets” section in the figure below will vary by design choice.
In the Open Compute Project, the BoW (Bunch of Wires) specification can also be regarded as a rival to UCIe.
3. With the help of PCIe and CXL standards, it can also be used for off-chip connections
The appearance and operation of the new UCIe interconnect are similar to on-die connections, and it also supports off-die connections with other components. These designs can even provide rack-scale designs with low latency and high enough bandwidth.
At the protocol layer, chip manufacturers have several different choices.
UCIe's official standard protocol is mature PCIe and open CXL (Compute eXpress Link, initiated by Intel).
PCIe protocol provides a wide range of interoperability and flexibility and has become the backbone of various other technologies; CXL can be used for more advanced low-latency/high-throughput connections such as memory (cxl.mem), I/O (cxl.io), and accelerators such as GPU and ASIC (cxl.cache).
customers and chip manufacturers can take advantage of their existing software investments in PCIe/CXL to further simplify the development process and launch UCIe-compliant chips faster. In addition, the alliance initiator has made it clear that UCIe will not be limited to PCIe/CXL, and its future versions may add other protocols.
Like other connectivity standards such as USB, PCIe and NVMe, the UCIe standard hopes to achieve ubiquitous and universality while providing excellent power and performance metrics for chip connectivity. The initial version of
UCIe was from Intel. In the past few decades, Intel has led the development of several highly-watched open interconnect technologies, including USB, PCIe, and Thunderbolt 3. Intel has also used AIB (Advanced Interconnect Bus) and UIB protocols for its EMIB.
Previously, when Intel attempted to cultivate a standardized chip ecosystem, it released a royalty-free open source AIB interconnection standard, but this did not gain enough industry appeal. By contrast, CXL is currently widely adopted, so it makes more sense to use it with UCIe.
However, UCIe and AIB are not inherently compatible (special subset designs can support both), so while Intel will continue to fully support the current AIB implementation, it will stop all further development and migrate to UCIe. The standard specification also includes a Retimer design that can extend the connection to outside the chip package , enabling optical and electrical connections to other components such as memory pools, computing and accelerator resources.
UCIe Alliance envisions this interconnection that ultimately enables the sufficient number of rack-level decentralized systems the chip industry has been working hard to build for decades. Die-to-Rack connections can use local CXL for PCIe communication (no conversion required), which may eventually provide the latency and bandwidth required for such designs, and other types of protocols can be used if necessary.
In the Open Compute Project, the BoW (Bunch of Wires) specification can also be regarded as a rival to UCIe. The
BoW specification is also designed to popularize chip designs and have impressive performance specifications, but it is not that flexible. For example, BoW provides energy efficiency ranges from 0.7 to 0.5pJ/bit (Picojoules per bit), while UCIe provides support from 0.5 to 0.25pJ/bit, which may vary depending on the process node used.
BoW supports fixed 16GT/s, while UCIe is configurable and expandable to 32GT/s. UCIe also leads in other metrics, such as Shoreline bandwidth density (1280Gbps vs 3.8Tb/s), and is limited to MCP packages, while UCIe can support most 2D and 2.5D packaging options.
Conclusion: UCIe is just getting started, but the initiator has looked to the future
Overall, the UCIe specification is designed to make the encapsulated interconnect look as similar to the on-die interconnect as possible, while providing a large number of options to achieve nearly any type of performance or encapsulation technology required.
standardized interconnection is the first step to improve the wider verification, compliance and interoperability of any device, and the semiconductor industry has long lacked a widely accepted chip confirmation, verification and qualification process. The UCIe Alliance is very concerned with these aspects, and the initial UCIe 1.0 specification has a chapter dedicated to verification and built-in features to help these things. The powerful member companies of the
UCIe Alliance will begin developing the next generation of UCIe technologies, including defining chiplet form factors, managing, enhancing security and other basic protocols. They are also looking for more members to join in the hope of accelerating the change in how the industry delivers new products. Not only is the new standard for
not only available in an open manner, but its related companies will set up a formal alliance group to manage and further develop UCIe later this year.
Source: UCIe official website, tom’s HARDWARE, AnandTech
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