Author | Lian Yuhui
Due to the epidemic, TSMC's annual China Market Technology Forum has been held online, just as before, opened by TSMC President Wei Zhejia. He pointed out that the global output value of semiconductor industry will reach one trillion US dollars by 2030. While developing rapidly, it also brings many challenges. For example, because of geopolitical , the supply chain has simultaneously increased inventory and carried out local production. In addition, global customers have strong demand for mature process capacity, but only by working together to overcome the challenges of building mature process capacity is the high cost problem of building mature process capacity.
Luo Zhenqiu, head of China business and general manager of Nanjing factory, said that due to the progress of technology and the continuous evolution of semiconductor technology, our real life scenes are more exciting than the science fiction movies imagined more than ten years ago. For example, the facial recognition contact lenses worn by the male protagonist in " Mission: Impossible 4" released in 2011 have been implemented in reality.
Due to the epidemic, remote work teaching, online entertainment, and telemedicine have become the new normal of life. The overall usage rate of global telemedicine has even grown by 38 times. The G network and low-latency technology have allowed massive medical applications to be aggregated.
entered the 2022 TSMC China Online Technology Forum. As the previous one, Zhang Xiaoqiang, senior vice president of business development, Liu Xinsheng, senior director of the Special Technology Business Development Department, explained the future of mature processes, and Qin Yongpei, senior vice president of the operation organization, explained the TSMC manufacturing capacity planning link.
"Ask Xin Voice" exclusively directly and organizes the following sections: 7nm, 5nm, 3nm, 2nm advanced process progress, production base and capacity planning; special processes include power management chip PMIC, CIS image sensor, IoT chip, MCU essential technology embedded NVM, panel display driver chip technology and other technical blueprint planning.
TSMC capacity planning:
- 018-2022, the annual compound growth rate of TSMC's advanced process capacity is 70%.
- 022 5nm production capacity will be more than four times that of 2020 (the first year of mass production).
In addition to continuing to move towards advanced production technology, TSMC will also continue to expand its special process production capacity to meet customer needs. The capital expenditure of characteristic process capacity in 2022 will be 3.5 times the average value in the past three years.
- characteristic process capacity will continue to grow, accounting for about 45% in 2018 and is expected to reach 63% in 2022. Compared with 2021, the production capacity of the special process of 12-inch wafers will grow by 14% in 2022.
- tml1tml9 TSMC's total EUV machines account for 55% of the world's EUV machines.
- In terms of new wafer factory planning, TSMC built an average of two new factories each year from 2017 to 2019; from 2020 to 2023, six new factories were built each year. In addition to expanding new wafer fabs, TSMC has also continued to expand new packaging plants and expand global production bases. Calculate the calculation: TSMC has started to build seven new wafer factories: three wafer factories in Taiwan, two overseas wafer factories, and two new advanced packaging factories in Taiwan.
- nm process production base: established in Tainan Fab 18 Phase 5, 6, 7, 8 and 9; the 2nm process production base has been determined in Hsinchu Fab 20.
- TSMC has also expanded its production capacity of 7nm and 28nm in Taiwan, located in Kaohsiung Fab 22. Construction is expected to start in the second half of 2022 and mass production is expected to be carried out in 2024. In terms of advanced packaging, Zhunan Factory has also been expanded.
- overseas wafer factories:
- Nanjing 28nm process new 12-inch wafer factory under construction is expected to start mass production in the fourth quarter of this year;
- D Fabric manufacturing, TSMC's 3D Fabric system integration solution covers front-segment silicon stacking TSMC SoIC and back-segment advanced packaging technologies including InFO and CoWoS. With the continuous investment in 3D Fabric, TSMC is expected to start silicon stacking production in 2022, with production capacity exceeding 20 times that of 2022 in 2026; in terms of advanced packaging capacity, production capacity in 2022 will be more than triple that of 2018.
- TSMC's SoIC technology provides the industry's best Interconnect density, and is paired with InFO or CoWoS processes to help customers improve product efficiency. SoIC technology is expected to start mass production in the second half of this year, and the full series of integrated Fabric factories will enter mass production in 2023.
Overall, TSMC entered mass production in 7nm in 2018, entered mass production in 5nm in 2020, and entered the 3nm era in the second half of this year. The 2nm technology is expected to start production in 2025.
- nm process technology: from mass production in 2018 to now enter the fifth year, product application area. From mobile devices, CPU, GPU, and then expand to AI, Netcom, RF, consumer electronics, and automotive electronics, it is expected that by the end of this year, the cumulative number of customer films from the 7nm process will exceed 400.
- nm+4nm process technology: In response to strong customer demand, TSMC is constantly expanding its 5nm+4nm production capacity, and its product applications have also begun to diversify, from mobile, CPU, GPU to AI and Netcom. There will be more diverse product applications in the future. is expected to accumulate more than 150 customer films by the end of 2022.
- N4X process technology: It is expected to be mass-produced in 2023, with a 15% increase in efficiency and a 6% increase in chip density compared with N5, while maintaining design compatibility and complete IP reuse.
- In terms of yield, TSMC N5 mass production yield is currently better than N7 , and the yield of N4 will also reach the N5 standard.
- N3 process technology: 3nm will be mass-produced in the second half of the year. After N3 mass production, N3E will be launched as an extension of the N3 family to provide better speed and power consumption. Compared with 5nm, the N3E performance increases by 20% at the same power consumption and reduces power consumption by 35% at the same speed. It will be fully provided from Mobile to HPC applications. Compared with N5, the
- N3E process has an increase in speed, a 30% reduction in power consumption, and a 36% chip area, enhancing the product's advantages in new processes.
Zhang Xiaoqiang also introduced the innovation in 3nm technology. In the past, product design was limited by chip space, and design engineers were often forced to choose between chip speed, power consumption, and area. After TSMC's N3E was launched, this will no longer be a trouble.
It is worth noting that . The "TSMC FinFlex" design architecture was introduced for the first time in the 2022 technology forum. TSMC FINFLEX technology can provide a variety of standard component selections: the 3-2 fin structure supports ultra-high performance, the 2-1 fin structure supports the best power consumption efficiency and the transistor density, and the 2-2 fin structure supports the performance of both, accurately assisting customers in completing a system single-chip design that meets their needs. Each functional block adopts an optimized fin structure to support the required performance, power consumption and area, and is integrated on the same chip at the same time. Under this design, the design library can be optimized to achieve the ultimate optimization, so that N3E can perfectly combine process and circuit design, providing a larger product design space.
- N2 Process technology: The new transistor architecture will be adopted. Compared with N2 and N3E, the speed will increase by 15% at the same power consumption, or at the same speed, the power consumption will be reduced by 30%, and the chip density will also be significantly progress. N2 is expected to start mass production in 2025.
- N2's innovative features: On the high-performance computing platform, N2 will provide a power network (backside power) on the back of the wafer to fully support the integration of chiplets. These innovations can help customers improve the overall performance of the product, especially speed and power consumption. Overall, N2 will better meet the needs of innovative applications of semiconductor products in the future.
- transistor architecture and materials are constantly innovative and evolved: more than ten years ago, the 2D planner architecture evolved to today's 3D FinFET, and now N2 will enter the new Nanosheet architecture. After Nanosheet, the transistor architecture will continue to evolve and innovate, except that CFETs stack N FETs and P FETs, which can greatly increase the density of transistors. There are also many innovations in materials, including 2D semiconductor material , and 1D Carbon nanotube (CNT), etc. These new materials will further promote the progress of semiconductor transistors.
- new semiconductor materials: In high-speed chip design, metal exchanges between low resistance and low capacitance are becoming more and more important. TSMC is developing a new process process , using mental-RIE, which can form a vacuum (airgap) between wires, reducing the effective capacitance of wires by 20~30%. In terms of wires, copper has been the dominant material in recent decades. When the thickness of copper wires is smaller than that of electrons, the resistance value will increase sharply, which is an obstacle to the evolution of semiconductor technology in the future. Currently, TSMC is working on a new 2D material that has the opportunity to replace copper as a wire. Since 2D materials have unique conduction properties, the resistance will not be affected by thinning of the wire, thus ensuring the high-speed computing performance of the chip.
- In terms of TSMC 3DFabric, the 2D InFO platform can achieve the integration of different chiplets in small package sizes and improve computing efficiency; the 2.5D CoWoS platform is suitable for integrating advanced logic chips and high-bandwidth memory HBM to meet high-performance computing needs such as AI and machine learning.
TSMC SoIC uses chip-on-wafer technology to achieve high-density chip stacking. SoIC, InFO, and CoWoS can be combined to provide different system integration methods.
- CoWoS technology platform: It can closely integrate different advanced logic chips and high-bandwidth storage HBM. CoWoS started with silicon interposer. As a connection, different interposer technologies have been developed for different products, including organic interposer (CoWoS-R and CoWoS-L), integrating organic interposer and embedded interposer/interconnect to achieve more systematic optimization. Furthermore, high-density capacitors are also embedded in the interposer to improve the overall computing efficiency of the chip.
- D SoIC chip stacking development plan: It adopts chip-on-wafer or wafer-on-wafer stacking technology to perfectly combine 3D chip stacking technology and transistor stacking technology, greatly accelerating future system computing capabilities. TSMC gave an example of the new generation of data center CPU processor EPYC that cooperated with AMD, fully demonstrating the importance of SoIC 3D technology. Through SoIC technology, AMD stacks Cache, Memory, and SRAM on the CPU chip, which has achieved record-breaking performance in many applications.
Regarding TSMC's progress in special technology processes, Liu Xinsheng, senior director of the Special Technology Business Development Department, pointed out in the technology forum that logic technology is crucial to enhancing computing capabilities. Special process technology is usually the key to connecting the real world and the digital world, including RF, connectivity, CIS, MEMS, power management chip PMIC, etc. In order to support the development of the entire semiconductor industry, TSMC provides a wide range of technology combinations, from advanced logic, special processes to 3D IC technology, etc.
Liu Xinsheng used two examples to illustrate the rapid growth of the special process technology. First, smartphones are fast and omnipotent. We hope to keep power forever. Whether it is sensing, sound, display, or power supply, it requires more special processes. The other is the smart car Smart Car, which is like a supercomputer equipped with wheels. A car has hundreds of semiconductor chips , including engines, hybrid mode, airbags, entertainment, network connections, etc.
In response to the increase in customers' demand for special process processes, TSMC has also continued to invest in special process technologies, with an annual compound growth rate of investment amounts from 2016 to 2021 exceeding 40%.
For special semiconductor process technology, low operating voltage Low Vdd and low leakage Low leakage are very important.
- Internet of Things IoT technology: The top priority is to provide ultra-low power consumption solutions and optimize the performance and power consumption of IoT and AI. The latest N12e process is suitable for edge computing chip . At the same time, Ultra Low leakage SRAM is also developed on the N12e process, with leakage current below 0.5pA/cell. Furthermore, the next generation of N6e process of is under development.
- G and wireless network N6RF process technology: In the dissemination of various videos, WIFI 7 has become very important, three times faster than WIFI 6. However, if adopts the same process as WIFI 6, the chip area of WIFI 7 will be 2.25 larger than WIFI 6, and its power consumption is 2.1 times that of WIFI 6. Therefore, smartphones, smart wearable devices, and AR/VR require better power consumption and area processing technology to reflect the advantages brought by WIFI 7 transmission speed. TSMC is expected to introduce the N6RF process, which can reduce the power consumption of WIFI 7 chip by 49% and the area by 55% compared to the N16 process.
- embedded NVM: This is the basic technology and application of MCU, and is used in smartphones, smart portable devices, automotive electronics, etc. At the same time, new embedded memory technologies such as RRAM, MRAM, etc. are also developed.
- RRAM: A cost-effective NVM solution, fully compatible with 40nm, 28nm, 22nm, and 12nm processes.
- MRAM: Suitable for high performance and high stability to solutions, such as industrial and automotive MCUs. 22nm MRAM will start producing IoT products in the fourth quarter of 2020, and its certification will also reach automotive Grade 1. 16nm MRAM is expected to be used for consumer electronics in 2022 and is expected to pass automotive Grade 1 certification in 2023.
- power management chip PMIC: various applications have increasingly wider demand for PMICs, such as wireless charging, automotive smart LED lighting, RF PA power packet tracking and other applications. In order to meet the increasing demands, TSMC has also upgraded the wafer production of PMIC to a 12-inch BCD process.
- In terms of power management chip PMIC, the technology that has been popular for many years is the 8-inch 0.18 BCD process. In addition, TSMC provides 12-inch BCD process from 0.13 microns 8-inch to 22nm. The next step is N90BCD. It is expected that mass production of will begin in the second half of 2022. The PDK version 1.0 has been released and the basic IP is ready.
- Image Sensor CIS: The rapid development of CIS is due to the advent of smartphones. The next wave of growth momentum will be automotive electronics and AR/VR. The key to Smart Sensing is high-quality lenses, multi-sensor fusion, and AI images. It also requires excellent pixel technology and low-power processing technology to provide a complete solution on the system.
TSI stressed that its CIS technology focuses on system level, covering CIS pixels, ISPs and stacking technologies for chip integration. The next step is to enter Multi-Wafer Stacking, so that customers have more choices to integrate CIS chips.
In terms of CIS sensors, TSMC's most advanced 28nm pixel technology can be used, and the bottom ISP has been expanded to N12 FFC. Furthermore, new image sensing requires the integration of new algorithms, and TSMC has also developed new stacking technology that can integrate Sensor and ISP to provide the highest efficiency at the system level.
Display Display technology: 5G and AI applications pursue high resolution and low power consumption, and more and more 5G smartphones use OLED smart panels. The next generation OLED panel driver chip needs more logic and SRAM, so it is inevitable to embark on the 28nm process.
