Converting analog signals from the "real" world to digital signals that can be processed upstream is a basic function of electronic systems, ranging from recording to Internet of Things (IoT), Industrial Internet of Things (IIoT), and now intelligence Internet of Things (AIoT). However, in order to use and execute effectively, we need to have a certain degree of understanding of its basic principles and operating procedures, which are often ignored by people.
For example, assuming that the amplitude of a typical analog signal applied to the analog-to-digital converter (ADC) input is constantly changing, how does the signal "hold" and then "sample" before conversion? Will the end of the signal conversion be different from the beginning? This amplitude variation or deviation can cause serious errors, especially for high-resolution ADCs that require more time for signal conversion. The challenge for designers is to understand and eliminate this source of error.
This article describes how to use ADC's sample and hold (S&H) or track and hold (T&H) circuit to prevent amplitude deviation. The S&H (or T&H) circuit will perform real input sampling, and the working interval is between the input anti-aliasing low-pass filter and the ADC. This article discusses the characteristics and selection criteria of S&H ICs, and introduces ADCs with integrated S&H. For the convenience of description, we used samples provided by Texas Instruments, Maxim Integrated and Analog Devices with different characteristics for different applications.
The role of sample and hold circuit in ADC
When a non-DC signal is applied to the ADC input, it will continuously change its amplitude. However, the analog-to-digital conversion process requires a certain time interval during which the amplitude of the ADC input will change (Figure 1). It is this amplitude deviation that leads to potentially serious errors.
Figure 1: Due to the change of the input signal amplitude during the digitization period (bottom), the ADC amplitude error (top) is caused. (Picture source: Digi-Key Electronics)
At this time, preventing the amplitude deviation in the ADC becomes a problem of how to sample the signal and maintain a fixed amplitude during the conversion process. This can be achieved by using S&H or T&H circuits for the ADC (Figure 2).
Figure 2: The main difference between the S&H (left) circuit and the T&H (right) circuit is the duration of the tracking period: S&H is shorter, and T&H is longer. (Image source: Digi-Key Electronics)
Both types of circuits sample the input signal and keep the sampling voltage constant during the conversion process. The T&H circuit output (right) tracks the input signal until the sample signal is sent; then the sampled value is saved during ADC conversion. S&H has a shorter sampling aperture and its output is a series of sampling levels (left). The main difference between T&H and S&H is the duration of the tracking interval: that is, S&H is shorter and T&H is longer. Both circuits rely on fast switching to isolate the energy storage capacitor connected to the signal input. In the remainder of this article, S&H will be used to refer to S&H or T&H.
S&H stage will perform real input sampling, and the working range is between the input anti-aliasing low-pass filter and ADC. The low-pass filter implements anti-aliasing band limitation and must precede S&H so that the signal can be band-limited before sampling to prevent aliasing (Figure 3).
Figure 3: In the digitizer signal path, S&H is placed between the anti-aliasing low-pass filter and ADC. (Picture source: Digi-Key Electronics)
Please note that the signals before S&H are all analog signals. The output of S&H is a sampled waveform that is fed to the ADC.
A typical S&H device
Texas Instruments LF398MX/NOPB S&H integrated circuit (IC) block diagram shows the basic circuit configuration (Figure 4). S&H is implemented using fast switching and high-quality capacitors. For LF398MX/NOPB, the capacitor is outside the IC. When the switch is closed, the capacitor is charged to the input signal voltage level. When the switch is off, the capacitor maintains this voltage until it is digitized by the ADC. This S&H uses bi-FET technology, which combines FETs and bipolar transistors to support fast speed with high DC accuracy (typically 0.002%) and extremely low voltage drop (usually less than 83 microvolts per second (µV)) Sampling (less than 6 microseconds (µs), the amplitude error is 0.01%). The internal amplifier buffers the switch and hold capacitor. The sampling time of
S&H depends on the value of the holding capacitor, which may range from 0.001 to 0.1 microfarad (µF). The external holding capacitor must have low dielectric absorption and low leakage capability. It is recommended to use polystyrene, polypropylene and polytetrafluoroethylene capacitors.
Figure 4: Texas Instruments LF398MX/NOPB S&H block diagram shows the key components: fast switch and external holding capacitor. (Image source: Texas Instruments)
S&H Features
S&H devices have many specific terms used to describe their operations (Figure 5).
Figure 5: The definition of common S&H dynamic characteristics includes sampling time, settling time, aperture time and amplitude drop. (Image source: Digi-Key Electronics)
The sampling time refers to the time from switching to sampling mode to S&H starting to track the input signal. It is a function of the value of the holding capacitor and the series resistance of the switch and the signal path. When the mode returns to the hold state, there may be a delay before the device stops tracking the input and starts to hold the value—this is the aperture time. Aperture time is a function of driver and switch propagation delay. Aperture uncertainty or jitter is the difference in aperture time due to clock changes and noise.
Once entering the hold mode, there will be a period of time between entering this mode until the holding value of the device stabilizes within an error band. This time is the so-called setup time or hold setup time. During some part of the settling time, there may be unnecessary charge transfer between the switch driver and the holding capacitor; this is called holding jump or pedestal error. The amplitude of the hold transition is usually in the millivolt (mV) range, and its impact can be minimized by keeping the full range signal as high as possible. The shortest sampling period of
S&H is the sum of sampling time, aperture time and settling time. The maximum possible sampling rate is the reciprocal of the sum of the sampling time, aperture time, and settling time.
In the hold mode, the hold value of S&H may decrease due to the leakage of the hold capacitor. This increase in voltage is called voltage drop. It is usually expressed as the rate of decrease in mV/sec.
S&H Configuration
S&H IC has a variety of configurations to meet various application requirements. Take an application that requires differential input as an example, such as the need to connect a differential output sensor such as an accelerometer, strain gauge, or optical current monitor. Maxim Integrated DS1843D+TRL is a good example of S&H IC suitable for this application (Figure 6).
Figure 6: Work like thisAs shown in the circuit, Maxim Integrated DS1843+TRL is a differential S&H, which uses double holding capacitors to achieve differential sampling. (Image source: Maxim Integrated)
shows DS1843+TRL for a typical optical line transmission application, in which it is used for burst mode received signal strength index (RSSI) measurement. Maxim Integrated DS1842/MAX4007 is a current monitor that can mirror the current from an avalanche photodiode connected to its reference input. The output current passes directly through the resistor RIN and converts it into a voltage. Then the voltage is measured differentially by DS1843, which includes a fully differential sampling switch, capacitor CS, and differential output buffer. This S&H uses two 5 picofarad (pF) capacitors, one capacitor is connected to the positive differential input and the other is connected to the negative differential input. The low capacitance value ensures fast sampling time. The fast sampling time of this device is less than 300 nanoseconds (ns). The hold time of this S&H is greater than 100 µs.
The devices on the market can accommodate four or eight S&H circuits in a single IC package. For example, SMP04ESZ-REEL four-channel S&H from Analog Devices. SMP04ESZ-REEL is a CMOS device that contains four S&H circuits in a common package with a sampling time of 7 µs and a drop rate of only 2 mV/s (Figure 7).
Figure 7 also shows how S&H is used with a digital-to-analog converter (DAC). In this case, it can prevent output transients or glitches caused by code conversion in the DAC.
Figure 7: Analog Devices SMP04 four-channel S&H contains four independent S&H circuits and matching buffer amplifiers. The circuit shown uses SMP04 to multiplex the output of the DAC to four channels. (Picture source: Analog Devices)
In the picture, SMP04 is used to multiplex the output of the DAC, dividing a single DAC output into four multiplexed channels. The S&H circuit can be used to selectively delay the output of the DAC until after the glitch, thereby smoothing the output of the DAC.
By pipelining the multiplexed input, multiple S&H circuits can be used to improve the throughput of the ADC. Here, multiple S&Hs are connected to the multiplexer output in common. The ADC is connected to an S&H, which holds the input level for conversion. Other S&Hs will acquire other multiplexer channels and then connect to ADC in turn, while the first S&H can be freely connected to other multiplexed channels. This pipeline processing technique eliminates S&H sampling time in the ADC signal path.
Many ADCs have integrated S&H or T&H circuits in their integrated packages. For example, the ADC121S021CIMFX of Texas Instruments is a 12-bit successive approximation register (SAR) ADC with built-in T&H, with a sampling rate of 50 to 200 kilosamples per second (kS/s). It uses a high-speed serial output bus, which simplifies the wiring layout (Figure 8).
Figure 8: Texas Instruments ADC121S021 is a 12-bit single-channel SAR ADC with built-in T&H circuit. (Image source: Texas Instruments)
This ADC is a typical representative of many integrated ADC circuits because it has internal T&H, which simplifies the layout of the printed circuit board and helps minimize the number of components. External T&H circuit is used for special configuration, such as for differential input connection, multiplexed input, or used inWhen ADC does not have internal T&H or S&H circuit.
Summary
From audio recording to the most advanced IIoT or AI analysis, converting analog signals into digital signals is the most basic electronic function, which requires special attention S&H or T&H circuit. In order to minimize the voltage deviation during the analog-to-digital conversion process, these circuits are essential because they can keep the ADC's input voltage constant during the conversion process. S&H can be located inside or outside the ADC, but it must be located in the signal path between the anti-aliasing low-pass filter and the ADC. As mentioned earlier, there are many configurations to meet the needs of various design applications, and each IC has single-channel, differential or multi-channel options. Applications can also be extended to include preventing output transients or glitches caused by code conversion in the DAC.
Source: Digi-Key
Author: Art Pini
2020 New Product Selection Guide free access
statement : article by the author Original, the content of the article is the author’s personal opinion. The reprint of the article is only used to convey a different point of view. It does not mean that the article agrees with or supports the viewpoint. If you have any objections, please contact the article.
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