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Text | Semiconductor industry vertical and horizontal
Recently, a hot event that has attracted much attention in the semiconductor industry is Samsung officially announced the mass production of 3nm process chips. In fact, before the official news was released, the industry had been discussing this matter, and the focus was the yield issue. As Samsung is sparing no effort to catch up with TSMC, Samsung has almost exhausted all its efforts. This time, before TSMC is about to mass-produce the 3nm process in the second half of the year, it has announced mass production first, which has a strong sense of competition. However, judging from the situation in recent years, in terms of advanced process technology , it has been repeatedly crushed by TSMC. A very important reason is that Samsung cannot guarantee the yield rate, which is a big minus in terms of gaining customer confidence.
A few years ago, when the 10nm and 7nm processes were just mass-produced, Qualcomm Snapdragon 845 SoC was produced by Samsung. Snapdragon 855 and 865 were produced by TSMC's 7nm process. Nvidia originally planned to produce the 7nm process by Samsung. GPU chips have also been transferred to TSMC. At that time, Samsung was lagging behind TSMC in terms of yield rate, and its order volume was significantly less than its competitors.
In 2021, the 4nm process will rise. Qualcomm will transfer the production order of Snapdragon 8 Gen1 Plus to TSMC. The important reason is that the yield rate of Samsung's 4nm process is only about 35%, which is higher than TSMC's yield rate of more than 70%. Too much difference.
In February this year, Korean media Infostock DAIly reported that Samsung Electronics suspected that the output and yield reports of its wafer foundry had been falsified. Therefore, Samsung's DS department was criticized by the management consulting department for its wafer foundry. The investigation of 5nm process yield will be followed by 4nm and 3nm investigations. The cause of the incident was that Samsung's wafer foundry business suffered from low yields. Especially after the mass production of the 4/5nm process, the yield rate was extremely low and the delivery time was continuously delayed, which caused Samsung executives to doubt. An executive familiar with Samsung Electronics' internal situation said: "As the volume delivered by the foundry business is difficult to meet recent order needs, we are skeptical about the yield of non-memory processes, which is known to be based on the yield (referring to previous good results). "The data in the yield report) can meet the order delivery." The suspects of the management consulting department are current and former executives of the DS department. The investigation includes: whether the yield report submitted previously is authentic and the actual flow of funds used to improve yield. Where.
In June this year, Samsung appointed Kim Hong-shik, vice president of the Memory Manufacturing Technology Center, to lead the foundry technology innovation team. Through the reorganization, Samsung mobilized memory chip experts to lead the core unit of the foundry business. This time, the reorganization of the wafer foundry department is also to improve the yield rate of 3nm chips and strive to overtake TSMC.
The reason why TSMC can lead the world in advanced manufacturing processes is its high yield rate. It is reported that three quarters after the company's 7nm process started mass production, its defective rate dropped to 0.09 per square centimeter. In the early stage of mass production of the 5nm process, the defective rate was lower than that of 7nm in the same period, and the defect density was approximately 0.10 per square centimeter. ~0.11. With the advancement of 5nm chip mass production, the defective rate has dropped below 0.10.
Another major chip giant, Intel , is also suffering from yield problems. In July 2020, the company announced that the 7nm chip originally planned to be launched at the end of 2021 had a decline in yield due to defects in the process, and the release time was delayed. 6 months. Prior to this, Intel had encountered many difficulties during the research and development of the 10nm process, resulting in multiple delays and mass production was only achieved in early 2019.
In summary, the importance of chip yield is evident.
A brief analysis of chip yield
Simply put, chip yield is the ratio of the number of qualified chips on the wafer to the total number of chips. The larger the value, the greater the number of useful chips, the less waste, the lower the cost, and the profit. The higher. The
yield can also be subdivided into wafer (silicon wafer) yield, die yield and packaging and testing yield. The product of these three yields is the total yield. Total yield is the core secret of all fabs and is difficult for outsiders to know. It can reflect the overall level and revenue capabilities of this fab in manufacturing chips.Every stage of
chip manufacturing, from wafer manufacturing, mid-range testing, packaging to final testing, will have an impact on the total yield. Among them, wafer manufacturing is the main factor affecting the yield. The yield rate of
is also affected by factors such as equipment and raw materials. To reach a higher level, it is necessary to stabilize the process equipment and restore process capabilities regularly. In addition, environmental factors will have an impact on the three yield rates mentioned above, such as dust, humidity, temperature and light brightness. The chip manufacturing and packaging and testing processes need to be carried out in an ultra-clean working environment.
In addition, the size of the wafer will directly affect the yield. Generally, the yield in the center area is higher and the yield in the edge area is lower (this is determined by the manufacturing process). The larger the wafer size, the larger the proportion of the central area to the total area, and the higher the yield. The yield rate of
is not static, it will improve as the process technology continues to mature. Generally speaking, when a new process technology is first put into mass production, the yield rate is relatively low. As production advances and the factors leading to low yield rates are discovered and improved, the yield rate will continue to improve. The yield rate of more mature production lines can be Reaching more than 95%.
Many semiconductor companies have engineers who specialize in yield improvement. In the wafer factory, there is a dedicated yield improvement (YE) department, and the yield engineer is responsible for improving the wafer yield; in IC design companies, the operations department has professional The product engineer (PE) is responsible for improving yield.
What can I do to save you? My yield
Chip yield is so important that the whole industry is paying close attention to it. Wafer factories, IC design companies, semiconductor equipment and material manufacturers, and industry scientific research institutions are all conducting various research and exploration to provide Contribute to improving chip yield.
Of course, the main battlefield for improving yield is still the wafer factory (IDM factory or wafer foundry). To improve the yield, we first need to deeply study the relationship between chip yield and reliability, and reliability is directly related to chip defects. Therefore, reducing the number of defects in the chip production process can improve the baseline yield and at the same time improve the device reliability.
In order to improve reliability, time, money and related resources need to be invested to improve yield. This requires a trade-off, because different types of chips have different requirements for reliability and the corresponding resource investment is also different, which will also directly Affect profits. For example, the reliability requirements of consumer electronics chips are not that high (compared with industrial and automotive chips). Therefore, after reaching a certain yield rate for this type of chips, the wafer factory will not pursue higher standards. , but allocate resources to develop the process and equipment of the next node, which can improve the profitability of mature nodes. For chips with high reliability requirements (such as automotive chips, the reliability requirements are two to three orders of magnitude higher than consumer chips), the wafer factory must pursue a higher benchmark yield level, which requires improvements in process technology and Invest more resources in equipment. However, there is a contradictory relationship between high performance and high yield, and it is difficult to balance both.
For wafer fabs, most of the systemic issues affecting yield have been resolved. Actual yield losses are mainly caused by random defects in process equipment or the environment. In order to detect reliability defects, the fab's production line must have corresponding process control equipment and inspection sampling mechanisms. The defect detection system used must have the required defect sensitivity, be well maintained, and meet specifications. Inspection sampling must be frequent enough for process steps to quickly detect process or equipment excursions. In addition, there must be sufficient detection capacity to support accelerated anomaly detection. In the actual operation process of
, a common difficulty is to accurately find the source of the benchmark defect. Sometimes, the defect is detected after multiple process steps after it is generated. This places high demands on the equipment monitoring system and mechanism. If it is not done well, , often cannot find the source of the problem. In order to solve this problem, the system will first inspect a wafer, run it in the designated process equipment, and then inspect it again. Any new defects found in the second inspection must have been produced by the designated process equipment. In this way, The root cause of the defect can be found.Therefore, setting up a sensitive detection mechanism can reveal and solve the random yield losses originating from each process equipment.
In addition, the wafer fab can classify the defects that appear on each device and generate a database that can be used as a reference for failure analysis of field failures. This method requires very frequent device authentication (at least once a day).
Through the above measures and methods, the wafer factory can effectively control defects and thereby improve chip yield levels. Of course, in addition to these, there are other ways for fabs to improve yield, so I won’t go into details here.
In addition to process control of the wafer factory production line, semiconductor material manufacturers upstream of the industry chain, especially silicon wafer manufacturers, can also provide guarantees for improving yield rates at the wafer level through innovative technologies.
For example, scientists from the Korea Institute of Machinery and Materials (KIMM) under the Ministry of Science and Information and Communications Technology of South Korea and Nanyang Technological University in Singapore (NTU) developed a technology-new nanotransfer-based printing technology (Nanotransfer-basedprinting), It can produce highly uniform silicon wafers. They combined a chemical-free adhesive printing technique with metal-assisted chemical etching, which can be used to enhance surface contrast to make nanostructures visible.
This nano transfer printing technology works by transferring gold (Au) nanostructured layers onto a silicon substrate at relatively low temperatures (160°C) to form highly uniform wafers with nanowires (nanowires) , to achieve control of the required thickness during the manufacturing process. This technology allows for rapid, uniform, and large-scale manufacturing of wafers. At the same time, the manufactured wafers have almost no defects and the chip produced has a very high yield. In laboratory tests, it was able to transfer 99% of a 20nm-thick Au film onto a 6-inch wafer. When using this method to process 6-inch wafers, the results showed that the printed layer remained intact and had minimal bending during the etching process, demonstrating the excellent uniformity and stability of this Nanotransfer-basedprinting technology. The
KIMM-NTU team believes that the technology can be easily scaled to 12-inch wafers, which is the mainstream wafer size in the production lines of fabs such as Samsung, Intel, TSMC and GlobalFoundries.
The debate between performance and yield
When talking about chip yield, we have to talk about performance, because there is a contradictory relationship between the two. In an era when consumer electronics chips are becoming popular, the yield rate has an absolute upper hand, because consumer electronics products do not have such high performance requirements. However, with the weakening of the consumer electronics market in recent years, correspondingly, the high-performance computing (HPC) and automotive electronics markets have developed rapidly and have huge potential. However, these types of chips have extremely high performance requirements. At this time, the yield rate cannot be achieved. No concessions are made, because under the absolutely high-performance mass production requirements, the yield cannot be as high as that of consumer chips.
In this way, various new chip architectures have emerged. The most representative and extreme one is Cerebras’ wafer-level large chip.
In August 2019, artificial intelligence startup Cerebras Systems released the Cerebras Wafer Scale Engine (WSE) processor, which is an extremely large chip made from a 12-inch wafer. Traditional chips are very small, and three to four hundred chips can be produced from a 12-inch wafer.
WSE has 1.2 trillion transistors and is specially developed for AI tasks. This giant chip has an area of 42225 square millimeters .
Normally, wafer factories will not manufacture such large chips because some impurities usually appear during the processing of a single wafer. The impurities will directly affect the chip yield. The larger the individual chip, the lower the overall yield. . For chips as large as Cerebras, yield assurance is a prominent issue. However, Cerebras Systems said it designed its chips with redundancy and that one impurity would not render the entire chip unusable.
In April 2021, Cerebras Systems launched an upgraded version of WSE, WSE-2, integrating 2.6 trillion transistors. The company said it designed a system that could bypass any manufacturing defects to achieve 100% yield, and initially, Cerebras had 1.5% extra cores to allow for defects.The reason why there are super large chips like WSE in
is that the high-performance computing market is more sensitive to performance than price. The main customers of the high-performance computing market are not the C-side, but the B-side industry customers. They are more sensitive to cost. Insensitive, most concerned about performance. Especially in recent years, the application of AI in the cloud computing market has been surging. The customers of cloud AI chips are mainly Internet giants such as , Google, and . In the eyes of these giants, computing power is king, and they have no regard for the computing power of and . The pursuit is almost endless, which is completely different from the consumer electronics market that believes in "enough is enough".
Of course, chips like Cerebras Systems's are extreme cases, and for the most part, chip sizes for the high-performance computing market are still within the traditional range. However, the conflict between yield and performance continues unabated. New solutions are needed.
At this time, Chiplet emerged as the times require, and it is unique in taking into account performance and yield. If you want to improve performance, you must reduce off-chip communications, and if you want to improve yield, you must ensure that the area of a single chip cannot be too large. The Chiplet solution can take both of these aspects into account. Chiplets can reduce the area of a single die (to ensure yield) and integrate different die using advanced packaging technology. In this way, communication between chips does not need to go through the PCB board and can be carried out within the package, which greatly reduces the cost of off-chip communication. AMD was the first to commercialize the chiplet solution in data centers and achieved good results. After seeing the business opportunities, Intel also followed up and developed a complete set of advanced process technology and packaging technologies.
In short, today with the continuous iteration of advanced processes, chip yield issues have become more and more prominent. At the same time, high-performance requirements are also causing trouble for yield rates. Everything is so difficult, and there will probably be fewer and fewer manufacturers that can handle this.
