On September 21, US startup Zyvex Labs announced that it will launch the world's highest resolution lithography system - ZyvexLitho1. The tool uses scanning tunneling microscopy to achieve atomic accuracy patterning and sub-nano resolution.

On September 21, US startup Zyvex Labs announced that it will launch the world's highest resolution lithography system -- ZyvexLitho1. The tool uses scan tunnel microscope to achieve atomic precision patterning and sub-nano resolution.

In fact, this technical principle is very simple. We can simply understand that when the scanning tunneling microscope is working, the needle tip current passes through the Si-H surface, which can break the Si-H bond, so that selectively etches away the hydrogen atoms on the Si-H surface, and obtaining the exposed Si dimer lines can reach the sub-nanometer resolution (0.768 nanometers--Si (100) 2×1-H dimer row width).

Therefore, it is actually a direct writing system (that is, writing with a pen, stroke, stroke), while the EUV lithography machine of ASML is an exposure lithography system, similar to taking pictures on mobile phones. Do you think it is possible to use a fountain pen instead of a mobile phone camera?

Let's take a look at the basic principle of Zyvex's " direct writing lithography machine " in detail: the diagram on the left of the figure below, when the scanning tunneling microscope works in AP mode (only tunneling current), it extends the specific crystal direction of the Si (100) 2×1-H dimer row to achieve selective Si-H surface etching.

Zyvex's " direct write lithography machine " has two working modes:

1. 1px can be realized in AP mode, that is, 0.768 nanometer resolution .

2, comparison, if FE mode (field emission mode) is used, the scanning etching resolution can only reach 4px, that is, 4nm resolution.

We can see from the parameter table of AP mode that its scanning speed is 20 nanometers per second .

Let's take a look at the enlarged photo. This is the only 0.7-nanometer resolution 5px*5px square etch pattern given in Zyvex's data. The size of this square is about 4nm*4nm.

According to the scanning speed of the AP mode, the scanning time for building such a pattern is about 1 second .

Of course, this "lithography speed" of building a small 4-nanometer block in 1 second is obviously unable to replace the current exposure process lithography machine.

Not only that, Zyvex's "lithography machine" only showed a 0.7-nanometer linear resolution , and did not show the prototype of building any 0.7-nanometer semiconductor chip .

So, The American company's 0.7nm line resolution "lithography machine" cannot replace ASML's EUV lithography machine .

In fact, the current naming of logic chip processes, such as the familiar 7nm chip and 5nm chip, are just the manufacturer's promotional names, and do not refer to the actual physical size.

For example, 5 nanometer logic chip , its characteristic size, the actual physical size of the metal spacing MP is 28 nanometers, which is the working range of the current NA0.33 EUV lithography machine .

For example, ASML currently uses EUV lithography machine NX:3600 for 5nm and 3nm logic chips with resolution of 13nm.

and the actual physical size of the metal pitch MP of of

It is reported that in 2023, ASML will be delivered to Intel next-generation high-NA EUV lithography machine. ASML is not idle either. It is currently actively participating in the research of the next generation of super-resolution lithography machine technology. still has no clear direction for .