Recently, at the 2022 Beijing Microelectronics International Symposium and IC WORLD Conference, Bao Yungang, a researcher at the Institute of Computing Technology, Chinese Academy of Sciences, Bao Yungang introduced the development of RISC-V and Chinese Academy of Sciences RISC-V open source processor "Xiangshan" and other related situations in the conference report.
According to reports, Xiangshan’s second-generation Nanhu architecture plans to tape out in the first quarter of 2023. The target is 14nm 2GHz. It is expected that the SPEC 2006 score will reach around 20.
Bao Yungang said that Xiangshan is currently the highest-performing open source RISC-V processor core in the world. Currently, the "two-core" development goals of Xiangshan classic core and Xiangshan high-performance core have been determined. The
classic core is based on the second-generation Xiangshan (Nanhu) engineering optimization, benchmarked against ARM A76, and provides the CPU IP core for pan-industrial fields such as industrial control, automobiles, and communications. The high-performance core is based on the performance improvement of the third-generation Xiangshan (Kunming Lake), benchmarked against ARM N2, and provides high-performance CPU IP cores for data centers, computing facilities, and other fields.
Xiangshan's first-generation core "Yanqi Lake" was taped out on July 15 last year. It is based on the 28nm process, with a die area of 6.6 square millimeters , a single-core L2 cache of 1MB, and an estimated power consumption of 5W.
Why do you want to be Xiangshan?
RISC-V was born in 2010. Today, there are hundreds of commercial or open source RISC-V processor cores registered on the RISC-V International Foundation website. Why do we need to build an open source, high-performance RISC-V core?
Regarding this issue, Bao Yungang said that we have communicated with many industry companies and done a lot of research and analysis, which made us judge that the industry needs an open source, high-performance RISC-V core. On the other hand, we are also thinking about a question - why is there not yet an open source mainline like Linux in the CPU field? Open source Linux was born in 1991, exactly 30 years ago. Today, Linux is not only widely used in industry, but has also become an innovative platform for academic circles to conduct operating system research.
RISC-V is an open source instruction set, but ten years have passed and it has not yet formed an open source mainline like Linux. The BOOM goal of Berkeley is a high-performance open source RISC-V core, but the BOOM code repository is relatively closed. Officials recommend that others implement any functions to communicate with them in advance to ensure that it does not conflict with their plans. According to the official statistics page of GitHub, from January 2014 to the present, only 8 people have submitted more than 100 lines of code modifications to BOOM. It can be seen that, to a certain extent, due to BOOM's strict external contribution policy, the open source community does not have a high degree of participation in BOOM.
Therefore, Dr. Tang Dan from the team and I have always believed that we should establish an open source RISC-V core mainline like Linux, which can be widely used by the industry and support academia to experiment with innovative ideas. The most important thing is that it must survive for at least 30 years like Linux!
Thus, "Xiangshan" was born. What is the level of
Xiangshan?
Xiangshan is an open source RISC-V processor core, and its architecture code is named after the lake. The codename of the first version of the architecture is "Yanqi Lake", which is a name given by students with a strong National University of Science and Technology plot, because they all spent a year in Huairou Yanqi Lake as a graduate student. The "Yanqi Lake" RTL code was completed in April 2021, and is planned to be taped out in July based on the TSMC 28nm process. The current frequency is 1.3GHz. The codename of the second version of
is "Nanhu", which is a tribute to the 100th anniversary of the founding of the Party. "Nanhu" plans to tape out at the end of this year and will use SMIC's 14nm process with a target frequency of 2GHz.
What open source license does Xiangshan choose? This issue has troubled us for quite some time. Later, we specifically asked Professor Zhou Minghui of Peking University for advice, and our friends developed 4 open source license plans. After repeated comparisons and weighings, we finally selected the solution ① in the following table - Mulan loose version license (MulanPSLv2). Here, special thanks to Mr. Zhou Minghui of Peking University for his professional guidance.The initial development speed of
Xiangshan was very fast: the code warehouse was established on June 11, and the out-of-order pipeline was completed on July 6, and CoreMark could be run correctly in less than a month; Linux started correctly on September 12; and Debian started correctly on October 22.
What follows is more than half a year of structural optimization, performance tuning, and timing optimization. The Xiangshan architecture is almost equivalent to a reconstruction. A typical example, Xiangshan's first version of branch predictor (BPU) refers to BOOM's BPU, but the back-end evaluation frequency can only reach 800MHz (TSMC 28nm). So Gou Lingrui, who was in charge of BPU design, continued to optimize the BPU structure under the guidance of several teachers, and finally increased the frequency to 1.4GHz.
During this period, friends took matters into their own hands and developed various optimization and debugging tools, which greatly accelerated the optimization and verification process. This makes me really admire these post-90s generation - they are really full of creativity, from work to life, and one of the main driving forces is "save (tou) time (lan)". For example, I would rather write a program to automatically order takeout than turn on my phone to read the menu.
How will Xiangshan develop in the future?
Currently, Xiangshan is developing the next-generation architecture "Nanhu", with the goal of tapeout by the end of this year. Based on SMIC's 14nm process, the frequency will reach 2GHz, and the SPEC CPU score will reach 10 points/GHz. This is a very challenging goal and requires significant optimization and improvement of the architecture.
A few days ago, my friends went to Jiaxing Nanhu to discuss the future development of Xiangshan. In addition to technology, we once again focus on processes and platforms. The previously built agile design process and platform supported a development team of more than 20 people, which was far from enough. What we need to consider now is how to build an open source, open, and standardized open process that can support the joint development of an open source community of 2,000 people.
supports thousands of people to develop open source software together, which has already had successful experience. But how to support thousands of people to develop open source processors together, there is currently no case that can be used as a reference, and we can only rely on ourselves to explore.
We have a wish - we hope that "Xiangshan" can survive for 30 years; we have a promise - we will get together in 30 years and see what Xiangshan will become. However, there are still many problems and challenges that need to be solved to realize this wish.
