Editor's note:
As one of the newest companies in the semiconductor EDA field, Shunyao EDA recently jointly created the "Chip Industry Observation" column with Zhang Tongshe. By combining the cognition and views of media people and chip industry practitioners, it aims to share the current situation and trends of the semiconductor industry for readers, and welcome to leave a message and communicate.
In recent years, the view that " Moore's Law " is about to end is popular, and "post-Moore era" has become a hot word in the industry. The question that follows is, how can we continue to improve the chip performance under the existing process, while keeping the cost unchanged or reduced?
, which is in the hot spot, is Chiplet technology , is regarded by many industry insiders as an opportunity for Chinese semiconductor companies to overtake after Moore's Law slowdown. Especially after Huawei was sanctioned by the United States and its advanced chips were restricted, Chiplet attracted much attention from the market. According to Omdia report, by 2024, Chiplet's market size will reach US$5.8 billion, and by 2035, it will exceed US$57 billion. Chiplet's global market size will usher in rapid growth.
In fact, Chiplet is not a new concept. Its concept originated from the multi-chip module born in the 1970s. That is, consists of multiple homogeneous or heterogeneous smaller chips, which are composed of large chips , that is, the chip originally designed in the same SoCh was split into many different chips. It was manufactured separately and then packaged or assembled. Therefore, the split chip is called "chiplet".
In 2015, Dr. Zhou Xiuwen, founder of Marvell, proposed the concept of MoChi (Modular Chip) at ISSCC 2015, which is the earliest prototype of Chiplet. In recent years, this concept has blossomed and bears, and international chip giants such as AMD, Intel , TSMC, and Nvidia have all begun to join Chiplet. At the same time, as more and more companies join the market, more and more design samples are also increasing, and the development costs are also beginning to decline, greatly accelerating the development of the Chiplet ecosystem.
01.Chiplet: The new magic weapon that continues Moore's law
At present, mainstream system-level single chip (SoC) is used to produce multiple computing units responsible for different types of computing tasks on the same wafer through lithography. As a representative of advanced packaging technology, Chiplet has embarked on a completely different path from traditional SoCs. It disassembles complex chips into a group of small chip units with separate functions, die (die chip) , and combines the module chip and the underlying basic chip package through die-to-die, similar to building Lego building block , forming a system chip to achieve a new form of IP multiplexing. The development and rise of Chiplet technology is not only a need for technological development, but also a driving force for economic laws. Nowadays, the R&D cost of mobile phones with a single product shipment of hundreds of millions of yuan often reaches or more than , and the shipment and profits in the Internet of Things segment are difficult to cover such R&D investment. To this end, the chip industry is actively exploring the Chiplet technology that decomposes SoC and multi-chip heterogeneous integration in a single package to balance the contradiction between rising R&D investment and declining shipments.
From the comprehensive view of its technical characteristics and current progress, the advantages of Chiplet are mainly attributed to several aspects : First of all, Chiplet can greatly improve the yield of large chips. At present, the huge computing demand in high-performance computing, AI and other aspects has driven the rapid increase in the number of computing cores in logic chips. At the same time, the supporting SRAM capacity and I/O number are also greatly increasing, and the number of transistors in the entire chip has soared. Through the Chiplet design, super-large chips can be cut into separate chips according to different functional modules and manufactured separately, which can not only effectively improve yields but also reduce costs due to defective rates.
Secondly, Chiplet can reduce the complexity and design cost of design.If is decomposed into core particles according to different functional modules during the chip design stage, some of the core particles can be designed similarly to modular and can be repeatedly used in different chip products. This can greatly reduce the difficulty and design cost of chip design, and at the same time it is conducive to subsequent product iteration and accelerate the product launch cycle.
In addition, Chiplet can also reduce the cost of chip manufacturing. After the SoC is chipledized, different core particles can be selected to select appropriate processes to manufacture separately according to needs, and then assembled through advanced packaging technology. There is no need to use advanced processes to integrate the manufacturing cost on a wafer, which can greatly reduce the manufacturing cost of the chip.
Although its advantages are outstanding, not all chips are suitable for using Chiplet. In many cases, a single integrated system chip will be more valuable. In comparison, AI chips have the highest requirements for chip design scale and require integration of high-bandwidth memory, high-speed I/O, high-speed network and other modules. The Chiplet architecture generally adopts a 3D integration solution, which reduces the chip area and expands the space. It is the best and most economical design for AI chips.
In addition, there are more and more domestic semiconductor startups that make "big chips" such as CPU and GPU. With more and more functional integration requirements and higher performance requirements, the challenges faced by design are getting bigger and bigger. Chiplet can realize the separation of different functional modules, evolve in stages according to their respective optimal iteration rhythms, effectively reducing the difficulty of R&D.
Chiplet is also very suitable for car autonomous driving chip . Since the automotive autonomous driving chips have very high computing power requirements, the chip area is very large, the cost is very high, and the automotive-grade certification cycle is very long. Using Chiplet design can not only reduce design difficulty, improve yield, and reduce design and manufacturing costs, but more importantly, it can also provide higher safety and rapid iteration.
Under the trend of digital economy , various super-large computing power chips will be expected to take the lead in adopting Chiplet-based design implementation ideas and engineering practice methods. high-performance server/data center, autonomous driving, notebook/ desktop computer , high-end smartphones, etc. will become the main application scenarios of Chiplet in the next few years, leading the growth of this market.
02.UCIe: A key step in the interconnection standard
Although it has many advantages, Chiplet also faces many challenges. Due to the different interconnection ports and protocols between dies produced by different architectures and manufacturers, designers must consider many complex factors such as process processes, packaging technology, system integration, and expansion. At the same time, it also needs to meet the requirements of information transmission speed, power consumption, etc. in different fields and scenarios, making the design process of Chiplet extremely difficult. The biggest challenge in solving these problems is the lack of a unified interconnection standard protocol.
In addition, with the gradual development of Chiplet, the demand for interconnection between chip particles from different manufacturers will inevitably explode in the future. Therefore, before the technology matures and the business trend is formed, industry manufacturers need to build a "bridge" to standardize the Chiplet Internet interface.
In March this year, AMD, Arm, Intel, Qualcomm , Samsung , TSMC, Microsoft , , , Google , Meta, , Sun Moonlight , ten upstream and downstream companies in the semiconductor industry formed the UCIe (Universal Chiplet Interconnect Express) industry alliance. For the semiconductor industry, UCIe, which is full of stars, is launched, and means a Chiplet standard that can be promoted and popularized is here!
As an organization established by many semiconductor and technology giants, the UCIe Industry Alliance has launched the UCIe 1.0 standard. The UCIe 1.0 standard is established for Chiplet technology. It defines the interconnection between Chiplets in the package, and uses to realize the universal interconnection of Chiplets at the packaging level and the open Chiplet ecosystem.
This standard is a three-layer protocol. The physical layer is responsible for telecom , clock, link negotiation, sideband, etc. The die adapter layer (Die-to-Die Adapter) provides link state management and parameter negotiation for the core particles. It optionally ensures reliable data transmission through cyclic redundancy verification (CRC) and retransmission mechanisms. The UCIe interface is connected to the standard interconnection protocol layer through these two layers.
Previously, all manufacturers used exclusive customization technology to implement core-grain packaging, which brought high costs and resistance to the further popularization of core-grain technology. After the UCIe interface technology is standardized, terminal users can freely match chip parts from multiple manufacturers' ecosystems when creating SoC chip . This will accelerate the development of the open Chiplet platform and span the architecture and instruction sets such as x86, Arm, and RISC-V.
It is worth noting that one month later, mainland Chinese semiconductor companies such as core original microelectronics, Supermotor Technology, Xinhe Semiconductor, Xinyaohui announced their participation in the alliance, and UCIe welcomed the first batch of Chinese legions. Up to now, many domestic companies such as Moore Elite , Canxin Semiconductor, Yixin Technology, Xinyaohui, Niuxin Semiconductor, Xinyunling, Changxin Storage , Supermotor Technology, Him Computing, Shixin Electronics, Alibaba , OPPO, Aip Technology, Xindong Technology, Lanyang Intelligent , etc. have become members of the UCIe Alliance, injecting a shot of augmentation into the Chinese semiconductor industry that is focusing on Chiplet.
03. Advances in multiple ways to promote the development of Chiplet technology in China
For Chinese semiconductors, Chiplet is regarded as an advanced packaging technology with a relatively small gap between China and foreign countries, and is expected to lead China's semiconductor industry to achieve qualitative breakthroughs in the post-Moor era. Chinese companies have also made a difference in Chiplet, actively integrating into the UCIe ecosystem and moving towards the path of Chiplet R&D.
Huawei HiSilicon is one of the earliest manufacturers in China to try Chiplet. In 2014, the 64-bit Arm architecture server processor Hi16xx, a 64-bit Arm architecture server processor jointly developed by Huawei HiSilicon and TSMC, integrated 16nm logic chips with 28nm I/O chips, realizing a cost-effective system solution, which can be regarded as an early Chiplet practice.
In addition to Huawei, many other domestic semiconductor companies have also made surprising progress. For example, Xinyuan Co., Ltd. is expected to be the first company in the industry to launch commercial Chiplets. In recent years, it has been committed to promoting Chiplet technology and industry. Based on the two major design concepts of "IP chipization, IP as a Chiplet" and "chip platformization, Chiplet as a Platform", core original launched a high-end application processor platform designed based on the Chiplet architecture. At present, the 12nm SoC version of the platform has completed streaming and verification, and the iteration of the Chiplet version is underway.
ChipTong Technology , which has been working in the Chiplet field for many years, launched the first high-performance server-level graphics card GPU " Fenghua No. 1 " using Innolink Chiplet technology to modularly package Chiplets made with different functions and processes to become a heterogeneous integrated chip. In April 2022, it took the lead in launching the domestically produced and independently developed IP solution for physical layer compatible with UCIe standards - Innolink™ Chiplet. It is reported that this is the first cross-process and cross-package Chiplet (core particle) connection solution in China, and it has been mass-produced and verified successfully in advanced processes.
Cambrian released its third-generation cloud AI chip Siyuan 370 in November 2021. It is based on the 7nm process and is its first AI chip based on Chiplet technology. It encapsulates 2 AI computing chips (MLU-Die) in one chip. Each MLU-Die has independent AI computing unit, memory, IO and MLU-Fabric control and interface. It ensures high-speed communication between two MLU-Die through MLU-Fabric. It can achieve the combination of different computing power, memory and codecs through different MLU-Die combinations.
Moore Elite is also exploring the establishment of a SiP platform. Through the strictly selected SiP chips and the existing KGD die transition, unified chip production and quality control, and established a one-stop Chiplet R&D, production and sales collaboration platform, so that more chip companies can enjoy the services of SiP design and flexible production.
In addition to the above-mentioned manufacturers, the company such as Supermotor Technology and Xinyaohui, which have successively announced their participation in the UCIe Alliance, as well as many high-performance CPUs, GPUs and large AI chip startups that are silently using Chiplet technology to overcome difficulties. The domestic chip design and application industry chain are actively participating in the global Chiplet ecosystem to collaborate together to contribute to the improvement of relevant industry technical specifications and standards.
04. Dangers and Opportunities under the Chiplet Trend
Although Chiplet is showing many benefits and market potential, it still faces some difficulties and challenges that need to be solved to give full play to its effectiveness.
Among them, solves the interconnection standards only the first step. To truly combine Chiplets, ultimately, rely on advanced encapsulation. Currently, TSMC has CoWoS/InFO, Intel has EMIB, Fovores 3D, etc. Chiplet uses a variety of advanced packaging, while the UCIe1.0 standard does not cover packaging/bridge technology for providing physical links between chiplets. In the future, with the development of Chiplet technology, the interconnection between chiplets will eventually reach a higher density. To cope with the continuous improvement of advanced packaging functions and density, heat dissipation, stress and signal transmission are all major tests.
For chip design, although there is no need to design complex large chips based on Chiplet, decomposing the SoC into Chiplet and integrating it into a 2.5D/3D package will bring a significant increase in system complexity, which poses great challenges in system design.
chip test level splitting a large SoC chip into multiple core particles, which is more difficult than testing a complete chip, especially when testing some Chiplets that do not have independent functions, the test program is more complicated. At the same time, in order to improve the overall yield after sealing, Chiplet integration also puts forward higher requirements for testing and quality control, and also poses higher challenges to the finished FT test process and test equipment after sealing of wafer-level CP and Chiplet.
In addition to chip design, verification, packaging and testing, the EDA tool chain that supports Chiplet chip design and whether the ecosystem is perfect and sustainable are also key issues that need to be solved for the success of Chiplet technology. Chiplet technology requires EDA tools to provide comprehensive support from architecture exploration, chip design, physics and packaging implementation, etc., to provide intelligent and optimized assistance in various processes to avoid human introduction of problems and errors.
UCIe 1.0 is largely a "starting" standard, essentially only defining 2D and 2.5D chip packages without 3D direct die-to-die technology (such as the upcoming fooveros direct). With the emergence of 3D chip packaging, the stacking of different dies under the Chiplet concept will also face a series of simulation analysis and verification problems such as reliability, signal integrity, power integrity, thermal analysis, etc., and EDA and chip design manufacturers need to work together to crack it.
For this reason, Chip and Semiconductor launched the "3DIC Advanced Package Design Analysis Full Process" EDA platform as early as the end of last year. It is the industry's first unified platform for 3DIC multi-chip system design and analysis. It builds a fully integrated, outstanding performance and easy-to-use environment for users, and provides a 3DIC full process solution from development, design, verification, signal integrity simulation, power integrity simulation to final sign-up, and fully supports 2.5D Interposer, 3DIC and Chiplet design.
, established in April 2021, China EDA innovation "dark horse" Shunyao EDA not only uses the " China High-speed Railway " method to fill the technical gap in the current market of digital chip verification, and obtained customer orders within less than one year of its establishment, and has received positive recognition and recognition from customers.
At the CCF Chip 2022 conference held a few days ago, the company's founder Fu Yong analyzed the new challenges of Chiplet design methodology to digital verification at the domestic digital EDA toolchain technology forum, and introduced the efforts made by Shunyao to solve the needs of system-level high-speed verification and simulation.
At present, Shunyao EDA has launched the RTL high-speed emulator ShunSim. This high-speed emulator can realize the simulation verification of the super-large integrated circuit of 10 billion gates, and its efficiency is 10-100 times higher than that of traditional emulators on the market. The product has built-in a robust and secure simulation kernel Verilator that has been verified by a large number of commercial cases, and has broad commercial prospects and continuous iteration capabilities.
According to Fu Yong, ShunSim adopts intelligent compilation and segmentation technology, which can divide the design originally running on a CPU into several small modules, which enables ShunSim to fully utilize the parallel computing power of multi-server, multi-core, and is very suitable for Chiplet chip design.
At the same time, in order to improve the verification solution and enhance the chip verification efficiency, Shunyao has developed a new generation of system-level verification solution YAOVIP to help chip designers locate and discover problems faster and more accurately. Therefore, Xunyao EDA's platform-level chip verification solution built on these two product lines can provide professional digital verification solutions and service support for key chip designs such as Chiplet.
"As the successor of SoC, Chiplet is a good development opportunity for the domestic semiconductor industry. As an EDA manufacturer, Shunyao really hopes to have the opportunity to cooperate with various IP manufacturers, universities, and research institutes to come up with different technical solutions." As Fu Yong said, the emergence of Chiplet's new design technology is undoubtedly a favorable opportunity for the domestic integrated circuit industry to come from behind. The launch of the UCIe 1.0 standard will open up the last barrier for the interconnection of chips across manufacturers and help the development of the semiconductor industry.
However, the development of the Chiplet model still has a long way to go. It is not only a technological upgrade, including packaging and testing technology, EDA tools, chip architecture design, etc., but may also bring about a reconstruction of the traditional semiconductor industry chain. Faced with the subsequent explosion of Chiplet in the global market, Chinese semiconductor companies have to work hard to get to the forefront, and work together to produce first-class Chiplet products to improve my country's semiconductor production capacity on high-performance chips and stand on the big stage of the post-Moore era.
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