Recently, TSMC, together with NTU and MIT , announced that it has made significant progress in chips below 1nm, and the research results have been published in Nature.
This study proposes the use of semi-metal Bi as a contact electrode for two-dimensional material. It can significantly reduce resistance and increase current, making its performance comparable to silicon materials, helping the semiconductor industry to cope with the challenges of the next 1nm generation.
paper wrote that silicon-based semiconductors have advanced to 5nm and 3nm, and the number of transistors per unit area is close to the physical limit of silicon material , and their performance cannot be significantly improved year by year. Previously, two-dimensional material was highly expected by the industry, but it has always been hindered by problems such as high resistance and low current.
According to reports, the discovery was first discovered by the MIT team. Then TSMC optimized the "easy deposition process", while Wu Zhiyi, a professor at the Department of Motor and Optoelectronics at NTU, successfully reduced the component channel to nanometer size by using a helium-ion beam lithography system.
Now, major manufacturers are actively studying advanced processes.
At the beginning of the month, IBM announced that it had created the world's first 2nm process semiconductor chip , using GAA surround gate transistor technology. In terms of the core indicators of
, IBM said that the transistor density of this 2nm chip (MTr/mm2, how many million transistors per are 1 square millimeter ) is 333.33, almost twice that of TSMC's 5nm, and is also higher than the 292.21 MTr/mm2 of TSMC's 3nm process. In terms of performance, IBM said that their 2nm process has a performance of 45% higher than the current 7nm under the same power consumption, and the output performance is 75% lower than that of the same power consumption.
However, it is not difficult for IBM to mass-produce the 2nm process, because the technology is still in the laboratory stage and IBM does not have the conditions for mass production.
. On TSMC, in late April, TSMC updated its process roadmap, saying that its 4-nanometer process chip will enter the "risk production" stage by the end of 2021 and achieve mass production in 2022; the 3-nanometer product is expected to be put into production in the second half of 2022, and the 2-nanometer process is under development.
