The main purpose of integrated circuit testing (IC testing) is to distinguish qualified chips from unqualified chips to ensure product quality and reliability. With the rapid development of integrated circuits, their scale is getting larger and larger, the quality and reliability requirements of circuits are further improved, and the testing methods of integrated circuits are becoming more and more difficult. Therefore, research and development of IC testing are of great significance. As test vectors are an important part of IC testing, it is increasingly important to study their generation methods.
1, IC test
1.1, IC test principle
IC test refers to providing test stimulus (X) to the DUT based on the characteristics and functions of the device under test (DUT), and comparing the DUT output response (Y) with the expected output, thereby Determine whether the DUT is qualified. Figure 1 shows the basic principle model of IC testing.
According to the device type, IC testing can be divided into digital circuit testing, analog circuit testing and hybrid circuit testing. Digital circuit testing is the basis of IC testing. Except for a few purely analog ICs such as operational amplifiers , voltage comparators, analog switches, etc., most ICs used in modern electronic systems contain digital signals.
Figure 1 Basic principle model of IC testing
Digital IC testing generally includes DC test, AC test and functional test .
1.2. Functional test
Functional test is used to verify whether the IC can complete the work or function expected by the design. Functional testing is the foundation of digital circuit testing. It simulates the actual working status of the IC, inputs a series of ordered or randomly combined test patterns, acts on the device under test at a rate specified by the circuit, and then detects whether the output signal is consistent with the output signal at the circuit output. The expected graphic data is consistent to determine whether the circuit function is normal. Its focus is on the rate of graphics generation, edge timing control, input/output control and shielding selection.
functional testing is divided into static functional testing and dynamic functional testing. Static functional testing generally uses the truth table method to find stuckat faults. Dynamic functional testing is performed at a speed close to the operating frequency of the circuit. Its purpose is to verify the function and performance of the device at a speed close to or higher than the actual operating frequency of the device.
functional testing is generally performed on ATE (Automatic Test Equipment). ATE testing can provide test stimuli with complex timing based on the simulation waveforms of the device in the design stage, and perform real-time sampling, comparison and judgment on the output of the device.
1.3, AC parameter test
AC parameter test is to verify time-related parameters in time units. It actually measures the time relationship when the circuit is working, measuring such as operating frequency, input signal and output signal over time. changing relationships, etc. Common measurement parameters include rise and fall times, transmission delays, setup and hold times, and storage times. The AC parameters of greatest concern are maximum test rate and repeatability, followed by accuracy.
1.4, DC parameter test
DC test is based on Ohm's law and is a steady-state test method used to determine device parameters. It verifies electrical parameters in the form of voltage or current. DC parameter tests include: contact test, leakage current test, conversion level test, output level test, power consumption test, etc. Commonly used test methods for
DC testing include pressure current measurement (FVMI) and flow pressure measurement (FIMV). Test accuracy and test efficiency are mainly considered during testing. The quality of the circuit can be determined through DC testing. For example, the contact test is used to determine the open/short circuit condition of the IC pin, the leakage test can reflect the process quality of the circuit in some aspects, and the conversion level test is used to verify the driving ability and noise immunity of the circuit.
DC test is the basis of IC testing and the basic judgment method to detect circuit performance and reliability.
1.5, ATE test platform
ATE (Automatic Test Equipment) is automatic test equipment. It is an integrated circuit test system used for IC testing.Generally include computer and software systems, system bus control systems, graphics memory, graphics controllers, timing generators, precision measurement units (PMU), programmable power supplies and test benches, etc.
system control bus provides the connection between the test system and the computer interface card. The graphics controller is used to control the sequential flow of test graphics and is the CPU of the digital test system. It can provide information such as power supply, graphics, cycle and timing, and drive level required by the DUT.
1.6 Generation of ATE test vectors
For simple integrated circuits, such as gate circuits, the ATE test vectors can generally be completed manually according to the ATE vector format. For some ICs with high integration and complex functions, the vector data is huge, and it is generally impossible to directly write the required test vectors based on their logical relationships. Therefore, it is necessary to find a convenient and feasible method to complete the generation of ATE vectors.
In the IC design and manufacturing industry, design, verification and simulation are inseparable. One method of generating its ATE test vectors is to optimize and convert the simulation vectors based on EDA tools (including input signals and expected outputs) to form test vectors in ATE format.
Based on this, a vector generation method can be established. Use EDA tools to build device models, and establish a Test bench simulation verification platform to provide test incentives, conduct simulations, verify simulation results, store input incentives and output responses, and generate ATE vector files according to the ATE vector format. The principle is shown in Figure 5.
Figure 5 Schematic diagram of ATE vector generation
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