The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie

2024/05/2602:20:33 hotcomm 1984

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

SSD The current mainstream flash memories are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about it for now.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficient in execution. Features of

: fast transmission speed, small delay, and long life. Because each storage unit contains less information,

requires a higher cost per million bytes to produce. Due to the high cost, you will basically only see it on high-end enterprise-level SSDs and flow into consumers. The loose films that can be purchased on Taobao are basically non-original white films or disassembled films with damaged disks.

MLC = Multi-Level Cell, that is, 2 bit per cell, with four charging values ​​of 00, 01, 10, and 11.

therefore requires more access time than SLC, but each cell can store twice as much data as SLC. . MLC flash memory reduces production costs compared to SLC flash memory, but its transmission speed is slower than SLC flash memory, and its latency is higher than SLC flash memory.

features: average transmission speed, average delay, average life span

TLC = Trinary-Level Cell, that is, 3 bit per cell, with eight charging values ​​000, 001, 010, 011, 100, 101, 110, 111, so

needs to be compared MLC has more access time. Each unit can store 1/2 more data than MLC. The required access time is longer than MLC, the delay is higher than MLC, and the transmission speed is slower than MLC. The advantage of

TLC is that it is cheap and has the lowest production cost per million bytes, but it has a short lifespan. Features of

: low transmission speed, high latency, and short lifespan.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

TLC flash memory has the advantage of larger capacity and lower cost. For example, if the same transistor circuit is made into 16Gb SLC flash memory, then it can be made into MLC into 32Gb, and when made into TLC flash memory, it can have a capacity of 48Gb. This This greatly reduces costs for manufacturers. Profit comes from low costs, which is why TOSHIBA, IMFT, and SAMSUNG have been switching to TLC in large numbers. In a word: If you have milk, you are a mother.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

When we see manufacturers fooling us, we often see the concept of P/E. The full name of Program/Erase Cycle is actually the number of erasable times of flash memory. Simply put, if a 64GB flash memory has a lifespan of 3000P/E, Then the expected life of the factory is 3000X64GB of rewritable capacity. Whether it can withstand long-term data writing is still an unanswerable answer. The life of flash memory will always exist with the quality of RP.

The improvement of flash memory technology has pros and cons for TLC:

Disadvantages: The chemical bonds of the oxide layer on the gate of the basic memory unit are becoming increasingly difficult to control, causing the number of P/E times to decrease with the improvement of the technology. The number of P/E times for TLC About 1000.

Pro: The density and capacity of a single flash memory have been greatly improved. The reading and writing principle of SSD to flash memory is based on balanced wear, so TLC can rely on the increasing capacity to reduce the wear and tear of a single basic storage unit to improve the product. The service life of TLC's SSD is 512GB:256GB:128GB=4:2:1, so in one sentence: TLC would rather buy a big one than a small one.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

After buying Qunhui DS716+II, I found that this NAS supports SSD for reading and caching . Originally, a Jinsheng 128G SSD was used as the read cache for Seagate 8T HDD. As the HDD has more and more data, , the 128GB SSD is not enough to do the read cache. A bunch of SSDs at home are large-capacity disks, and I can’t bear to use them on the NAS, so I thought about buying a 240-256GB SSD from JD.com to use as a read cache for Qunhui. Using it, it seems that only Kingston UV400, OCZ T150, and Plextor M7V disks are available. I accidentally discovered that JD.com silently added a Liteon Ruisu V5S disk, but no one was interested. I became curious, and I am cheap. Just order one and come back to see what it is, and take a look at it.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The appearance of the SSD is actually not much to look at, especially SATA, which is just as expensive as the enterprise level.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The style of disassembling every time has never changed. With the blessing of the hair dryer, it is not very difficult to dismantle anything without affecting the warranty. Surprisingly, this PCB is indeed too small, which reminds me of The previously disassembled SanDisk SSD PLUS 240GB.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

Front:

Master: SMI 2258

Cache: Nanya NT5CC256M16DP-D1 (512MB DDR3 1600)

Flash: SKhynix H27QFG8PEM5R (64GB 16NM TLC) X2

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

Back:

Flash: SKhynix H 27QFG8PEM5R (64GB 16NM TLC)X2

This disk is a little special in that The 256GB disk uses a 512MB cache chip, and TLC does not use large OP operations to sell it as 240GB, but has a complete full disk capacity of 256GB. In terms of hardware structure, this is exactly the same as the S2, which is only released abroad by its brother Plextor, but the firmware may be different.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

For TLC flash memory support and error correction, the common masters on the market are the following:

Huirong SMI: SMI2258 SMI2260

Among them, INTEL 540S and 600P are the most representative

Phison PH: PS3111-S11

S11 master At present, the most commonly used control in China is the GALAXY Warrior series. Most of the flash memory is self-sealed TLC that is packaged by Phison and sold to GALAX.

Perfect MARVELL: MV 88SS1074

Among them, Kingston UV400 and Plextor M7VC are the most representative. Of course,

's exclusive controllers, such as the Polaris controller used by Samsung PM961 and the MEX MGX controller widely used by EVO, have quite mature support for TLC, but are limited to Samsung's own use.

From the main control point of view, I have used SMI’s main control quite a lot and have a relatively deep understanding of it.

SMI2246XT: The most well-known is SanDisk SSD PLUS 240GB, which has no cache but only supports MLC, so disks that use this kind of master control can only use MLC flash memory.

SMI2246EN: The most popular product, this controller can be seen in some products from Lianxing's ZETA series, to Plextor's M6V, to SanDisk SSD PLUS's 480GB products. The biggest advantage of this controller is The cost of the solution is low, and the performance is not so good. MLC is still a good choice. Since it does not support LDPC error correction and only supports BCH ECC error correction, it is not appropriate to use TLC. It is recommended to choose MLC products.

SMI2260: When talking about this NVME master controller developed for 3D TLC that supports LDPC software and hardware error correction, we have to talk about INTEL 600P. It is the recent sales star. It is the first time that INTEL sells an NVME product at such a conscientious price. Although the performance is Compared with SATA AHCI, it does not have an advantage, but it has made a huge contribution to the popularization of NVME SSD, and it has also played an important role in helping INTEL clear a large amount of TLC first-generation inventory. Although those who can afford the NVME disk look down on the 600P, the NVME 600P is only the price of a SATA disk, so the big Vs are shouting that the performance of this disk is terrible, but at the same time they are buying it up to support the surge in sales on JD.com.

SMI2258 is an AHCI master control developed for 3D TLC that supports LDPC software and hardware error correction. For improvements based on SMI2256, INTEL's 540S is one of the representatives.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

Reading is a very enjoyable and relatively painful process, especially reading quotes and excerpts. People will feel disgusted if they read too much, so simply extracting the characteristics and adding your own understanding is the most suitable way to read.

, the SMI2258 master control, has several obvious features:

1, better support for SLC CACHE

2, NANDXtend™

3 based on LDPC error correction, support for TLC and 3D TLC

4, and four channels each supporting a maximum of 8CE, for a total of 32CE. If

wants performance, you have to look at whether it supports the maximum tolerance of 32CE and whether it supports SLC. Cache

wants safety. LPDC error correction requires the era of

SLC flash memory. The particles are very good. Generally, an 8bit/1KB BCH ECC error correction is fine. Very strong

MLC flash memory era, the particle size is average, generally requires a 40bit/1KB BCH ECC error correction to be qualified. For example, Toshiba's explanation of the life of MLC:

24bits/1KB ECC can have 1000P/E times during error correction, 40bits/1KB ECC error correction can have 3000 P/E times. When the P/E times are reached, the data retention period is more than 1 year.

1, 24bits ECC error correction, when the P/E times reaches 1000 times, the data is stored for 1 year, the number of error bits in 1KB data is less than 24

2, 40bits ECC error correction, when the P/E times reaches 3000 times, the data is stored 1 After one year, the number of error bits in 1KB data is less than 40

3 and 24bits ECC error correction. When the number of P/E is greater than 1000 times, there is no guarantee that after one year of data storage, the number of error bits in 1KB data is less than 24

4 and 40bits ECC error correction. , when the number of P/E times is greater than 3000 times, there is no guarantee that after one year of data storage, the number of error bits in 1KB data will be less than 40

This is the relationship between the level of BCH ECC error correction and MLC flash memory P/E

Then it comes to TLC flash memory In this era, the granularity is getting worse, and BCH ECC error correction can no longer meet the requirements. This requires the use of LDPC hardware and software error correction to meet the data security requirements within the P/E cycle. The NANDXtend™ technology controlled by

SMI2258 is the integration of LDPC hard decoding, soft decoding and RAID data recovery.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

SMI claims that this technology can allow 600P/E TLC flash memory to run at a high temperature of 120 degrees. During the life of 1800P/E, the erroneous data can be corrected. This can actually be understood as:

LDPC hardware and software error correction, 600P/E When TLC erase is less than or equal to 1800P/E, silent errors discovered by CRC can be recovered by the RAID data recovery function. It is precisely because SMI has the RAID data recovery function that

is very bold in making a 256GB TLC full disk capacity instead of a 240GB TLC disk with 16GB OP.

But what I want to say here is that the LDPC error correction capability and RAID repair capability of the main control are only a threshold for us to evaluate TLC products. The performance and reliability of a disk depends on the strength of the firmware, but There is no need to talk about TLC without LDPC error correction!

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

SKhynix H27QFG8PEM5R’s flash memory properties appear from Hynix’s PDF to be Toggle 2.0 TLC flash memory manufactured in 16nm process, QDP 4Die stack, BLOCK size is 4M, capacity 512Gb=64GB.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

SKhynix H27QFG8PEM5 Because the R flash memory has few reference materials, I have modified the numbering rule diagram of Hynix myself, which can give everyone a reliable reference for this flash memory and Hynix flash memory. Although Hynix's particle numbering rules have changed over time and have already entered the 16nm TLC era, except for a few code changes, the numbering rules basically follow the numbering rules established in 2009. Since there are few Hynix particles on the market and the numbering rules are not well known to everyone, I will process the technical document into this particle number for understanding:

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

H=SK Hynix

2=flash

7=nand flash

Q=3.3V

FG=512Gb=64GB

8=Bandwidth X8

P=4 Die (QDP) + TLC + Large block

E=4 CE

M=First generation particle

5=FBGA132 package form

R=Lead-free and halogen-free

B=Contains bad blocks

C=Operating temperature 0-70

Then the red font is the key information, which The chips are 4Die 4CE, and the 4 flash memories make up a total of 16Die 16CE, which is just half of the maximum 32CE allowed by the SMI2258 master. This means that there will be higher speeds filled with 32CE on 512GB and 1TB disks. The

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

cache is Nanya NT5CC256M16DP-D1 (512MB DDR3 1600 C11). There is nothing much to say about the cache itself, but the SMI2260-controlled INTEL 600P 512GB also uses this cache chip, and this disk is only V5S 256GB. 256GB is used. A large cache with a capacity of 512MB has advantages and disadvantages. Advantages of

: The cache of SSD is mainly used to store FTL mapping tables. In addition, it also stores some page-sized data, as well as user data in merge optimization. Otherwise, there is no need to use such a large cache. The SSD will process every IO read and write. Query or update the real address of the flash memory from FTL. The response speed of the FTL table is fast but the size is huge. A 256GB SSD using 512MB cache can get a faster response speed than a 256MB cache, and the 4K read and write performance will be more stable. Effect.Disadvantages of

: A large external cache is very helpful to the performance and lifespan. While getting the benefits, the cost and risk are also very high. Optimizing the writing technology requires high power loss and the risk is very high. The larger the cache, the more likely it is to lose power when the power is lost. , the more likely it is that the data in the cache will be lost. We know that the cached DRAM chip is volatile. The SSD will continuously write the data in the cache to the flash memory to prevent data loss, but it is embarrassing. In this case, data loss happens to occur at the moment of power outage, and it happens to be the data in the cache. The amount of data lost at 256MB is only half of the amount of data lost at 512MB.

In fact, there are now more advanced DDR3 STT-MRAM, which is non-volatile. Just like NAND flash memory, it can retain cached data even if the power is turned off, and does not require the hard disk to refresh the cache content to the flash memory. This kind of DRAM is the most suitable. Yes, but the cost is too high, not to mention that whenever a new product appears to solve an old problem, a new problem will appear. Let’s just say it casually.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

AS SSD BENCHMARK is an SSD testing software that many people have used. Many people have criticized it. Many people have said that they have cheated. Many people cannot say that it has passed. Some people say it is a test artifact and some people say it is a junk cheating software. I just want to say one thing. Whether the software is garbage or a artifact depends on how you use it!

1, different CPUs have different bonuses.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

This disk is used on my X230 top-end notebook with I7 3520M, and the performance optimization in power management is turned on. The running scores are as above. This test actually has a points formula: total score = 0.08x continuous reading + 0.16x continuous writing + 2x4k reading + 1x4k writing + 1.5x4K QD64 reading + 1x4K QD64 writing

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

What if I use I7 6700K to run? This result shows that the power of the CPU has the greatest impact on the reading and writing of 4K results. Therefore, the 4K running score part of this software has a certain relationship with the power of your CPU. If the running score is low, don’t just ignore it. Look at your 4K scores and then look at your CPU, and you will understand.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

As we introduced before, the characteristics of TLC determine that reading and writing are slow, so most TLC SSDs are configured with SLC Cache to accelerate reading and writing. It is not a real SLC flash memory. Each basic storage unit of SLC flash memory only It stores 1-bit data, so the read-write speed is better than 2-bit MLC and 3-bit TLC. The essence of configuring SLC Cache for TLC SSD is to carve out a part of TLC space in the TLC flash memory, and only write 1-bit data into each basic storage unit. This part of the TLC space is simulated as SLC for data reading and writing to improve SSD performance. After the SLC Cache is full of data, it will write the data in the SLC Cache to the TLC flash memory, and erase the SLC Cache and write the data again. Although the algorithms of firmware from different manufacturers are different, the basic principles are the same.

Many students said that to expose the TLC prototype, you can just run the 10GB test block of AS SSD BENCHMARK. The principle is to expand the test data block to exceed the capacity of the SLC Cache to expose the performance of TLC. In fact, I would like to say that if you want to know more about the SLC CACHE mechanism of this disk, you can run it in this order: 3G 5G 10G. As soon as

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

3G runs, you will find that the continuous writing of this disk has dropped by half.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

runs 5G, continuous writing continues to drop.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

runs 10G, and continuous writing continues to drop.

This shows that continuous writing starts to plummet from the 3GB test block. It shows that the capacity of SLC CACHE is within 3GB. To determine the size of SLC CACHE, you need to find 3GB.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

In the 3GB test, when the continuous reading progress bar was halfway through, we found that the continuous writing speed was still above 486MB/S.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

After the progress bar is halfway past, the continuous writing speed drops to less than 300MB/S, indicating that at least the first 1.5GB is accelerated by SLC CACHE, so it can be determined that SLC CACHE is greater than 1.5GB and less than 3GB.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

Then continue to run an HD TUNE 10GB write test to see. There are a total of 10 grids of 10GB. After finishing the second grid, the writing speed begins to drop from more than 400 to 200MB/S, indicating that this SLC CACHE is the factory-set 2GB. Capacity size. It also fully complies with the test of SLC CACHE size between 1.5GB-3GB locked in front of AS SSD BENCHMARK.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

HDTUNE is basically very stable when running full-disk reading. Running full-disk writing is almost the same as running 10G writing.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

TLC SSD with SLC CACHE has two AS SSD BENCHMARK scores. One is the SLC CACHE state and the other is the TLC state. . After knowing that the SLC CACHE size is 2GB, it is relatively simple to obtain these two scores. When testing the SSD,

AS SSD BENCHMARK needs to write a certain amount of data to the SSD first to test the writing, and then test the reading. The default data size is 1GB, and the maximum is 10GB. If you use 1GB of data to test this disk, all the test files will be written into the SLC Cache. The tested writing performance is the writing performance of the SLC Cache. If it is read again, it is also the read performance in SLC Cache. So if you test some TLC, you will find that it is not weak at all.

1. The 1GB test block must be run three times continuously. The continuous operation means that the mouse clicks on START. After one test, click the next one immediately. The first time is the SLC Cache state, and the third time is the TLC state. The

SLC Cache capacity is 2GB. After running the 1GB test twice in a row, you can immediately run the third time to get the real speed of TLC. Because the SLC Cache has been exhausted by the third time and will not participate in the process of data read and write acceleration. , the writing result tested at this time is the real speed of TLC SSD.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

If running 3GB, run the 3GB data block test twice in a row. The first time is the state of SLC Cache mixed TLC, and the second time is the TLC state

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

. Then the main use of the above test is that we need to see the running speed of the TLC state. If you can accept the running score of the TLC state, then the running score of the SLC Cache state will be more acceptable. If the running score of the TLC state is too low for you, then be decisive and return it.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

Generally, the test scores you see are the AS SSD BENCHMARK running scores in the empty disk state.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

Then you need to understand how the speed will change as more and more data is written. That is what we often say, as the amount of writing increases, will the speed drop significantly? The simplest The method is to test when the disk capacity is close to full. I tested the SLC Cache status of the 1GB database when the disk was 92% full. When the

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

disk is 92% full, the test scores of the TLC status of the 1GB data block.

can find that there is no difference between the running scores of empty disk and 92% capacity. Whether it is SLC Cache or TLC status, the running scores and speed are almost the same. However, after NTFS formatting to 238GB, when there is more than 236GB of data in the disk memory, the status of the SLC Cache will directly change to the TLC status, but it is already close to the full disk status. This writing performance is actually meaningless. At this time, it is more important to What matters is read performance.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

IOMETER 128K QD32 under RAW is written continuously for 1 minute without partitioning. The setting diagram is as above.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

Then open the CSV file generated this minute and find that the average write speed is 147MB/S. Then divide the SSD capacity by this test result to get the time required to perform a 128KB sustained write operation twice the SSD capacity, (256GBX1024MBX2 )/(147MB)=3566 seconds=59.44 minutes.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

is slightly more relaxed and directly changes the template time of 128K SEQ to 60 minutes to fill the disk

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

and then performs a 5000-second 4K QD32 random write test.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

created a scatter plot

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

. After removing the peak in the first period and the sporadic peak scatter points, we can find that the lowest valley is also above 1000IOPS, and the main area is a dense area between 1500-5000IOPS, with an average value of 3342IOPS.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

Then the first peak may be the track of SLC Cache write release.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The average IOPS in the last 500 seconds is also 3234IOPS, which shows that during the 5000-second full-disk 4K QD32 writing process, the speed is basically constant. Although it is TLC flash memory, it does not produce serious write attenuation under strong write pressure.

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

The current mainstream flash memories of SSD are divided into SLC, MLC, and TLC. Of course, there are also 3D-V NAND and XPOINT. Let’s not talk about SLC = Single-Level Cell, that is, 1 bit per cell. There are only two charging values ​​​​0 and 1. The structure Simple but efficie - DayDayNews

For early TLC SSD disks, due to the firmware not being strong enough, the problems that occurred were quite obvious. Take the SMI main control as an example. When the SMI2246EN, which was an early test of TLC flash memory, was paired with TLC flash memory, there was a lot of curses and distrust. There are many calls for it. In the SMI2256 master control era, it was a learning period for TLC adaptation. SMI was also constantly learning how to control TLC. Only when SMI2258 and SM2260 master control SMI's control of TLC reached a mature stage, from a In the ordinary TLC disk test, you can feel that the strength of the firmware is the foundation of the TLC disk.

So as an ordinary consumer, we have to buy SSD when the price of flash memory increases by 20%. This must be a rigid need. So it is recommended to buy a few MLC SSDs before the tail of MLC runs away. Of course, if you think MLC is too It’s expensive. If you want to choose a relatively cost-effective TLC disk, you must at least consider the following aspects:

1. You need to understand the performance of this disk in the SLC Cache and TLC states, and the performance in the TLC state. You have to be able to accept it.

2. The main control must support LDPC error correction.

3. Is the firmware robust? Including the case where there is data in the disk, will reading and writing in TLC status slow down significantly?

4. It is recommended to choose TLC as the system disk. Choosing MLC for important data is not 100% reliable. It is recommended to make a backup. This is a foolproof strategy.

[Conclusion]

This article was written by "gaojie20", a netizen on What's Worth Buying, and authorized to be reprinted. Due to space reasons, only the best parts are selected for sharing. The complete original text can be found on our website "TLC is coming, can you still buy SSD with confidence?" 》Check it out. If you have more goodies you want to share with us, please feel free to interact with us in the comment area.

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