Preface
This document mainly introduces the rich hardware interface resources of the Allwinner A40i development board, as well as some precautions in development and design. Quanzhi's A40i development board is the latest representative work from Chuanglong Technology. Its core board adopts a "100% domestic + industrial grade" design, with exquisite appearance and high playability. In the situation where domestic chips are gaining momentum Next, is it really the first choice for electricity users? Lets come look! Because the content of
is too long, it is divided into three articles: upper, middle and lower. This article is the upper one and covers in detail: power interface, LED, BOOT SET startup selection DIP switch , KEY, serial port , CAN interface , Micro SD interface, SPI FLASH, RTC socket, etc. All embedded enthusiasts are welcome to pay attention and check it out.
development board hardware resource diagram 1
development board hardware resource diagram
A40i processor's IO level standards are generally 1.8V and 3.3V, and the pull-up power supply generally does not exceed 3.3V. When the external signal level does not match the IO level, A level conversion chip or signal isolation chip needs to be added in the middle. ESD design needs to be considered for buttons or interfaces. When selecting ESD devices, attention should be paid to whether the junction capacitance is too large, otherwise signal communication may be affected. The
USB interface
CON16 (USB1 HOST) and CON17 (USB2 HOST) are USB2.0 HOST interfaces, using a single-layer Type-A connector; CON18 (USB0 OTG) is a USB2.0 OTG interface, using the Micro USB connector .
USB1 HOST interface
evaluation baseboard expands the USB1 total line into 4 USB HOST buses through the USB HUB chip , and leads one of them to the USB1 HOST interface.
picture 66
picture 67
USB2 HOST interface
USB2 The HOST interface is directly derived from the USB2 bus.
picture 68
picture 69
USB0 OTG interface
USB0 OTG interface is directly derived from the USB0 bus.
picture 70
picture 71
design notes:
U23/PI14/USB0_ID needs to add a 47K resistor to pull up to VDD_3V3_MAIN. The
Ethernet interface
evaluation board contains 1 RGMII ETH Gigabit network port and 1 MII ETH 100M network port.
RGMII ETH Gigabit Ethernet port
CON19 is the RGMII ETH Gigabit Ethernet port, and the RJ45 connector has a built-in isolation transformer.
Note: The A40i processor integrates a GMAC controller and supports 1 RGMII Gigabit network port.
picture 72
picture 73
design notes:
- VDDL_1V2_ETH power supply is the internal output of YT8521SH-CA, please do not use it to power other loads. The
- XTAL_I and XTAL_O pins are connected to a 25MHz passive crystal oscillator. If you need to use the 25MHz active crystal oscillator , you can access it from the XTAL_I pin and leave the XTAL_O pin floating. The
- YT8521SH-CA chip requires that after the power supply is stable, it should be maintained for 10ms before pulling the reset signal high. It is recommended to refer to the reset circuit solution of the evaluation baseboard. If you need to use the IO control network port to reset, you can attach the R286 resistor.
MII ETH 100M network port
CON20 is MII ETH 100M network port, using RJ45 connector and built-in isolation transformer.
Note: The A40i processor integrates an EMAC controller and supports 1 MII 100M network port.
Figure 74
Figure 75
Design considerations:
- The XTAL_IN and XTAL_OUT pins are connected to the 25MHz passive crystal oscillator. If you need to use a 25MHz active crystal oscillator, you can connect it from the XTAL_IN pin and leave the XTAL_OUT pin floating. The
- YT8512H chip requires that after the power supply is stable, it should be maintained for 10ms before pulling the reset signal high. It is recommended to refer to the reset circuit scheme of the evaluation baseboard. If you need to use the IO control network port to reset, you can attach the R256 resistor.
4G module expansion interface
CON22 is a 4G module expansion interface, using the Mini PCIe slot. The evaluation baseboard expands the USB1 total line into a 4-way USB HOST bus through the USB HUB chip , one of which leads to 4G module expansion.
CON21 is a Micro SIM card holder, which adopts the card self-ejection method and does not have detection pins.
picture 76
picture 77
Design notes:
- In order to ensure a stable power supply for the 4G module, its 3.3V power supply needs to be independently powered by MIC29302S/TR (U55), which provides at least 2A current output . If you want to replace other power supplies, it is recommended to use LDO. For details, please refer to the 4G module data manual requirements.
- If you need to control the power supply of the 4G module, you can attach R282, R283 resistors and Q6 transistors, and use GPIO to control the power enable state of the 4G module. The
WIFI module
evaluation baseboard expands the USB1 total line into a 4-way USB HOST bus through the USB HUB chip , one of which leads to the expansion of the WIFI module. The onboard WIFI module (U42) model is Bilian BL-R8188EU2, which adopts stamp hole connection method.
CON23 is an SMA interface, used to connect the 2.4G antenna of the WIFI module.
picture 78
picture 79
Bluetooth module
evaluation baseboard expands the Bluetooth module through UART2. The onboard Bluetooth module (U74) model is Ebyte E104-BT5011A, which uses a stamp hole connection method. The module comes with a PCB on-board antenna, no external antenna is required.
picture 80
picture 81
SATA interface
J4 is a standard 7pin SATA hard disk interface.
Figure 82
Figure 83
Design Notes:
- SATA_ESTXP/M and SATA_ESRXP/M lines need to place a 10nF AC coupling capacitor close to J4. The
- SATA interface supports 1.5Gbps and 3.0Gbps rates. Currently, only the 1.5Gbps rate is tested normally.
SDIO interface
J2 is an SDIO interface, using 2x 6pin female header with a spacing of 2.54mm. The interface includes SDC3 bus, GPIO and 3.3V power supply, and can be adapted to the ATK-RTL8189 SDIO WIFI module.
picture 84
picture 85
expansion IO signal interface
J14 is a 2x 6pin pin header interface with a spacing of 2.54mm, which leads to SYS_RESETn, AP-NMIn, Audio Codec, GPIO and other expansion signals.
picture 86
picture 87
At this point, the hardware resources and precautions of the A40i development board have been basically shared.
