On the right of the picture is Jiang Shangyi.
Mainland China wafer leading foundry SMIC reported a major personnel earthquake on the evening of Thursday (11th). Vice Chairman Jiang Shangyi, co-chief executive Liang Mengsong and independent non-executive director Yang Guanglei fully quit. Board of Directors, Jiang Shangyi left SMIC. Although I responded that I wanted to spend time with my family, the market believes that the small chip (chiplet) technology that I insist on developing has not been adopted, or extreme ultraviolet (EUV) lithography cannot be obtained. Equipment related. However, the advanced packaging technology that SMIC has not paid much attention to has become an important driving force for TSMC, the world's leading wafer foundry, to move towards advanced wafer chips.
After the wafer foundry entered the advanced process field, whether Moore's Law can be maintained has become the focus of the industry. After entering the 7-nanometer process, it exclusively supplies EUV lithography equipment and the Dutch semiconductor equipment manufacturer ASML (ASML) Becoming an important key, TSMC first used 193nm immersion ArF lithography with deep ultraviolet (DUV) lithography equipment, allowing TSMC's first-generation 7nm process to be born. It also used EUV technology to continue to promote transistor shrinkage, and TSMC also took advantage of this to attract customers. The gap between and Samsung Electronics has widened. Even after the US semiconductor giant Intel vowed to return to the foundry business, it also announced that it would fully adopt EUV technology in the Intel 4 process.
However, recent news pointed out that due to TSMC’s 3nm process failure, Apple ’s next-generation iPhone processor A16 chip will continue to use TSMC’s 5nm process, creating a situation of using the same process for three consecutive years. TSMC also responded , did not comment on market rumors and reiterated that the 3-nanometer process is proceeding as planned.
TSMC is facing soaring production costs. According to "Business and Industry" reports, it has promoted improvement plans for extreme ultraviolet light (EUV), improved EUV machine design, and introduced advanced packaging, so that more customers are willing to use the 3-nanometer process. use.
According to a report last year by the WeChat official account of "Wenxin Voice" owned by mainland technology media DeepTech, Jiang Shangyi said that when he joined SMIC, he was not only familiar with Zhou Zi, the then chairman, but also had a passion for semiconductors. He said, "I am just a very simple engineer. I have the right to pursue my ideals and career goals, especially technical ideals. I am very familiar with Jay Chou, and we have talked for a long time, mainly because of I still have a strong enthusiasm for semiconductor . I am very passionate about advanced packaging technology and small chips (chiplets). It will be easier to realize my ideals at SMIC."
Jiang Shangyi pointed out that TSMC started doing advanced packaging because of his 2009. At that time, he only spent 1 hour explaining and Zhang Zhongmou . Zhang Zhongmou immediately approved and agreed to give 400 engineers and US$100 million in equipment to do it. At that time, no one could see this path. In the end, TSMC took the lead, and many people followed Jin, everyone agrees that this is the path that should be taken in the post-Moore era.
TSMC stated at last year’s technology forum that it would integrate its 3DIC technology platforms including SoIC (System Integrated Chip), InFO (Integrated Fan-out Packaging Technology), CoWoS (Chip on Substrate Packaging) and other 3DIC technology platforms, naming it “TSMC 3DFabric” to provide the industry with The most complete and versatile solution. Since TSMC announced its cooperation with Arm, the first 7nm chiplet system with CoWoS packaging solution and silicon crystal verification has been adopted by AMD, MediaTek , and even the new products released by AMD recently pointed out that the launch of cooperation with TSMC to create 3D chiplets The Milan-X series of 3rd generation EPYC processors adopt 3D V-Cache vertical stacking cache technology. Microsoft also announced at the event that it will adopt .
Therefore, Chiplet technology is regarded as a countermeasure to solve the failure of Moore's Law. Even if the process technology and shrink are facing cost and technical difficulties, multiple small chips are packaged into one SoC (system on a chip). However, there are still There are many technical issues to overcome, including heterogeneous integration of 3D stacking and close cooperation between chip design and packaging teams.
In this regard, EDA manufacturer Cadence launched the 3D-IC platform "Cadence Integrity", which can support TSMC 3DFabric technology, showing the focus of future advanced chips, and the importance of advanced packaging will become increasingly high. In other words, if SMIC really does not pay attention to chiplet technology and lets Jiang Shangyi die, it will be a heavy loss.
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