Author: DIGITIMES He Zhizhong
0 The global wafer foundry leader TSMC has made further arrangements and continues to "extend life" for Moore's Law. The supply chain has also been reported that Huawei's HiSilicon has recently been included in the first wave of cooperative operators. Zhunan's new advanced packaging factory is expected to provide capacity support in the future, and TSMC's speech system does not make public comments on specific products and customers.
Recently, TSMC Zhunan Advanced Packaging and Testing Plant has launched an environmental impact assessment plan. Those familiar with advanced semiconductor packaging industry said that TSMC has recently developed and promoted the extension of new technologies based on the 2.5D/3D IC packaging process, paying more attention to "elasticity" and "heterogeneous integration", and moving closer to the concept similar to system-level packaging (SiP).
System-On-Integrated Chips technology proposed by TSMC will provide chip operators with services that can more tolerate various design combinations, especially high-bandwidth memory (HBM).
TSMC has recently released a number of advanced packaging technologies in one go, including SoICs, WoW, etc. The supply chain has reported that Huawei has already established itself as a leader in the smartphone brand, and at the same time, for Huawei, which adopts the latest technology, its IC design HiSilicon continues to strive to adopt TSMC's advanced wafer manufacturing and advanced packaging processes, and is the first to introduce high-end chips with WoW packaging and HBM. The chip is packaged in wafer stacking, and also uses the TSV (silicon perforation) concept based on 2.5D IC. Since Huawei is expected to bring a large amount of energy in the future, and the development of integrated chips combined with efficient computing and artificial intelligence is a global trend, the establishment of the new factory in Zhunan is quite possible to give TSMC a stronger capacity support. However, TSMC and other related businesses do not comment on market rumors, specific products and progress.
In fact, people familiar with TSMC's advanced packaging said that the concept of SoICs proposed by TSMC is rooted in the 2.5D/3D IC packaging process CoWoS (Chip-on-Wafer-on-Substrate) that extends from the Wafer end and the later WoW package. SoICs relied on CoW (Chip-On-Wafer) design, mainly hoping to connect two bare chips with the same grain size (Die size) through wire technology in the field of advanced processes of 10 nanometers or less. In this way, for chip operators, the silicon intelligence (IP) used has been certified for one round, and can be more mature in production, with higher yields, and can also be imported into memory applications.
Of course, TSMC has a high yield of more than 90% in the wafer manufacturing end, but the challenge in the packaging part is that after the two sides are connected, the yield will relatively drop to about 81%. However, this is a major technological progress in the current or future system single chip (SoC) must be integrated into more functions, and the difficulty in miniaturization is getting higher and higher, that is, the physical limit is gradually coming, and advanced packaging methods can be used to "extend life" for Moore's Law.
market has also been reported that TSMC intends to continue to expand its advanced packaging combat power. Zhunan Factory has a good chance to become one of the new advanced packaging and testing bases. Currently, TSMC's advanced packaging such as InFO and CoWoS are mostly in the Longtan factory, and professional wafer testing (CP) is concentrated in Factory 7. Currently, TSMC's advanced packaging and testing plants are distributed in Zhuke, Zhongke, Nanke, Longtan and other regions.
TSMC continues to strengthen its advanced packaging layout extending from the wafer end (Wafer-Level). Those familiar with IC packaging and testing industry said that in terms of the CoWoS packaging process that has won high-end artificial intelligence (AI) and high-efficiency computing (HPC) chips of leading manufacturers such as NVIDIA, AMD, and Google, it is estimated that TSMC's monthly production capacity has expanded from the previous 70K to 200K (200,000 pieces), which is almost higher than the total of several major outsourced packaging and testing foundry (OSAT) operators. It is estimated that the monthly production capacity of Sun Moonlight Semiconductor 2.5D/3D IC packaging of Sun Moonlight Semiconductor under Sun Moonlight Investment Control is about 20,000 to 30,000 pieces, and silicon products are about 100,000 to 120,000 pieces, and Amkor's South Korean factory is only about 20,000 to 30,000 pieces.
semiconductor related industry insiders said that in the field of advanced packaging, TSMC has indeed gone quite fast. From CoWoS to lock in very high-end chips with low quantity and precision, InFO (integrated wafer-level fan-out package) extending from 2.5D technology, it has become famous for helping TSMC stabilize Apple AP orders.
TSMC binds advanced packaging with advanced wafer manufacturing process, focusing on "diamond-level customer" integration services, and will continue to strengthen its efforts. For example, the 12/10/7 nanometer chip binding CoWoS or InFO packaging has won orders from leading American companies. Therefore, in the field of extremely high-end chip products of first-tier chip manufacturers, TSMC does have a certain degree of exclusion for other OSAT companies in taking orders. However, from another perspective, TSMC, as the leader, has turned around and further driven the continuous evolution of advanced packaging technology in the global semiconductor industry. In the medium and long term, it still has a positive push for the overall semiconductor industry.
