Source: This article was compiled from CTIMES by Semiconductor Industry Observation, thank you!
TSMC finally revealed the technical architecture that its 3nm will adopt at its corporate briefing in the first quarter of this year. To everyone's surprise, they will continue to use the current "FinFET" transistor technology. This means that TSMC’s process scaling capabilities far exceed the market’s imagination, and 3 nanometers is still not its limit.
When the manufacturing process is lowered, the circuit will inevitably encounter control difficulties, resulting in short-channel effects (Short-channel Effects) such as leakage and voltage instability. In order to effectively suppress the short channel effect, increase the circuit area as much as possible and improve the stability of electron flow, it is an important consideration for semiconductor manufacturers, and the FinFET architecture was born.
FinFET uses a three-dimensional structure to increase the contact area of the circuit gate, thereby making the circuit more stable and achieving the goal of continuous shrinkage of semiconductor manufacturing processes. However, the shrinkage of this three-dimensional structure is not unlimited. Once it reaches a lower process, it must switch to other technologies, otherwise Moore's Law will stop here.
Therefore, Samsung Electronics (Samsung) announced in 2019 that it will switch to Gate-All-Around (GAA) technology in the 3-nanometer process generation as their successor process after FinFET; Coincidentally, Intel, the current semiconductor leader, also recently announced that it will invest in the development of GAA technology and is expected to launch a 5-nanometer chip using GAA process technology in 2023.
Since the world's top two semiconductor factories have successively announced their involvement in GAA, it is even more certain that maybe 3 nanometers will be the era of GAA, because by the 3 nanometer process, FinFET transistors may face bottlenecks and must be forced to On to the next generation.
Continuing to use FinFET architecture will bring a win-win situation
But TSMC alone will continue FinFET transistor technology in the 3nm generation.
And like all industries, TSMC’s selection considerations are also the result of business decisions. And their ability to make this decision means that they have confirmed that 3nm is not the bottleneck of FinFET technology, and they are even very confident that they can achieve a yield rate above the standard in the 3nm process using the same FinFET technology. This also means that TSMC’s shrink technology far exceeds that of other chip manufacturers.
Therefore, TSMC will enter the 3-nanometer generation under the same process technology and manufacturing process. Therefore, they do not need to change too many production tools and can have a more advantageous cost structure. For customers, there will be no need for too many design changes, which will also help customers reduce production costs. If the final product performance can still be on par with its competitors, then TSMC may be better in the 3nm product generation.
Especially for customers, changing the design in the development of advanced processes, whether it is changing the design tools or the verification and testing process, will be a huge cost, both time and money. Therefore, if the current design system can be maintained, it will be a win-win situation for TSMC and customers.
Chip performance determines market value How far can FinFET go? The remaining question for
is who has better performance, and the answer will only be known after the mass production of 3nm chips in 2022. Since the products with the most advanced processes are used in the highest-end products, the prices of these products are high, so the cost is relatively unobvious. Once the performance advantages cannot be highlighted, consumers will lose support and orders will be lost.
Samsung Electronics has faced this situation several times in the past. Although their prices are lower, the performance of their products has never been better than that of TSMC. Therefore, the first-class manufacturers have turned to TSMC to invest, causing them to frequently lose in the high-end wafer foundry market.
Therefore, after entering the 3nm generation, if Samsung's GAA process can outperform TSMC's FinFET in terms of performance, even if the price is higher, it may reverse the current market situation of advanced chip foundry.
The sheet structure of FinFET technology has successfully continued Moore’s Law, but how far can it go? .
Another question is how long can FinFET technology last? If 3nm is not the bottleneck, where is it?
Fortunately, there are only two possible answers left at present, if not 2 nanometers, then 1 nanometers. But no matter which one it is, we won’t know it until many years later. But we can judge from TSMC’s past speeches that they are quite confident in micro-minimization technology and believe that achieving 1 nanometer is not a problem and that 0.1 nanometer can be a challenge.
Comparing the strategies they adopted in the 3nm generation, we can boldly predict that we may not be able to understand TSMC's capabilities until the 1nm generation, but that is already a completely unimaginable super-advanced chip manufacturing technology.
New architectures are coming out one after another, 2nm process layout
However, the FinFET process will eventually reach its physical limit, and the layout of successor technology should also start to be planned. At present, it seems that the use of GAA technology that increases the gate circuit area will be Among the most likely options, Nanosheet FET will be the most suitable process. Samsung currently uses this structure as the core technology of its 3-nanometer generation.
Of course Nanosheet FET is not the only option. There are still many research institutions conducting research on chip process technology after 3 nanometers. For example, imec recently announced a technology called "Forksheet FET" for 2-nanometer chip manufacturing.
According to Amico's information, in the "Forksheet FET" structure, nFET and pFET are integrated in the same structure, with a dielectric wall separating nFET and pFET. It is also completely different from the current GAA process and will use different devices to produce nFETs and pFETs. The advantage of this technique is that it has a tighter n to p spacing and reduces area scaling. Compared with Nanosheet FET, the circuit of Forksheet FET is more compact (42nm vs 45nm) under the same process.
Compared with Nanosheet FET, under the same manufacturing process, the circuit of Forksheet FET is more compact. (Source: imec)
In addition, Imec is also developing a technology called CFET (Complementary FETs), which is another GAA architecture developed for processes below 2 nanometers. The technology consists of two separate Nanowire FETs (n-type and p-type). It is a structure in which p-type nanowires are stacked on n-type nanowires.
Through this form of superposition, CFET is equivalent to realizing a "folding" concept, thereby eliminating the bottleneck of n to p separation, while also reducing the area of the cell active area. Up to 2 times as much.
Currently, these technologies that are still under development have their own challenges to be overcome, including heat dissipation control and manufacturing costs. But what is certain is that for chip manufacturing after 2 nanometers, several technologies are currently in progress. At the same time, it won’t be out of reach.
Conclusion
Judging from the current divergent process technology adoption decisions, it is obvious that semiconductor manufacturers have faced the challenge of switching to new architectures for chip manufacturing after 3 nanometers, and there is still no dominant technology.
At this time, in addition to manufacturers needing to show their talents, how to obtain the largest niche from technology and cost will be the key to competition. In particular, the cost of manufacturing advanced semiconductors is very high. If a better balance between production technology and manufacturing costs cannot be achieved, future development will be very difficult. In addition, the semiconductor manufacturing supply chain is heavily involved, not only manufacturing equipment. , also includes design tools and inspection and testing parts. If there is no consistent solution, it will be very difficult to stand out.
*Disclaimer: This article is originally created by the author. The content of the article is the personal opinion of the author. The reprinting by Semiconductor Industry Watch is only to convey a different point of view. It does not mean that Semiconductor Industry Watch agrees or supports the view. If you have any objections, please contact Semiconductor Industry Watch.
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