“This year marks TSMC’s 35th anniversary. When we were founded in 1987, we had a total of 258 employees and launched 28 products across 3 technologies;

TSMC recently held its annual technology symposium in Santa Clara, California, and the presentation provided a comprehensive overview of their status and upcoming roadmap ( "TSMC's latest process roadmap, 2nm officially unveiled" ), covering process technology and All aspects of advanced packaging development. This article will summarize the highlights of the process technology update.

Some information shared by Wei Zhejia

"This year is the 35th anniversary of the founding of TSMC. When we were established in 1987, we had a total of 258 employees and released 28 products covering 3 technologies; ten years later, we have 5,600 employees, Released 915 products covering 20 technologies; by 2022, we have 63,000 employees and will release 12,000 products covering 300 technologies "

" from 2018 to 2022, 12-inch wafer (equivalent). The annual compound growth rate exceeds 70%. In particular, we saw a significant increase in the number of 'big die' products. In 2021, TSMC's North American business segment shipped more than 7 million pieces. 5,500 pieces. There are 700 new product tape-outs (NTOs). This segment accounts for 65% of TSMC’s revenue. Our gigafab expansion plan typically includes adding two new 'phases' per year - 2017-2019 is this. situation. In 2020, we opened six new phases, including our advanced packaging fabs, and 7 new phases in 2021, including wafer fabs in Taiwan and 2022. There are 5 new stages, both in Taiwan and overseas:

• N2 Fab: Hsinchu Fab20

• N3: Tainan Fab 18

• N7 and N28: Kaohsiung Fab22

• N28: Fab16

• N16 in Nanjing, China. , N28 and expertise: Fab23 in Kumamoto, Japan (2024 Year)

• N5 of Arizona (2024)

"Statistics of the installed EUV lithography machine systems around the world, TSMC owns 55% of them"

"We will significantly expand capital equipment investment in 2022." ( The chart below highlights the large increase in planned spending on capped equipment )

“We are experiencing manufacturing pressure on mature process nodes. In 35 years, we have never increased capacity on mature nodes after subsequent nodes are in mass production – but this is the case. Banker side is happening. We are investing to increase production capacity on our 45nm process. ” (Later, in a question and answer session with another TSMC executive, a reporter asked whether capacity expansion would be implemented on other mature nodes such as 90nm or 65nm. Their response was: “No, expansion plan Currently only targeting the 45nm node.")

"We continue to invest heavily in 'smart manufacturing' focusing on precision process control, tool productivity and quality. Each gigafab processes 10 million dispatch orders per day and optimizes tool productivity. Each gigafab generates 70B data points per day for proactive monitoring.

At the seminar, a special "Innovation Zone" was allocated in the exhibition hall for the first time. Products recently offered by some startups were highlighted. TSMC said: "We have increased support investments to help small companies adopt our technology." There is a dedicated team focused on startups. Support for smaller customers has always been a focus. Maybe somewhere in this space will become the next Nvidia.

TSMC’s 12 Key Milestones

In 1987, TSMC was founded with the creation of the PurePlay business model.

In 1999, TSMC became the first foundry to offer 0.18 micron copper technology.

In 2001, it brought the first foundry reference Design flow. TSMC spent a lot of money to create the massive EDA and IP ecosystem we enjoy today

In 2011, TSMC brought HKMG 28nm into the fabless ecosystem, so this is TSMC's creation. Node of record.

launched CoWos in 2012, the first heterogeneous 3DIC test vehicle.

In 2014, TSMC delivered the first fully functional FinFET network processor, ushering in today's FinFET era dominated by TSMC.

In 2015, TSMC passed the advanced 3DIC packaging technology InFo.

In 2018, TSMC made its most advanced logic technology (N7) available to everyone.

In 2020, TSMC led the industry with N5 EUV-based logic technology.

In 2021, TSMC launched N4P, N4X and N6RF.

In 2022, TSMC will launch the most advanced N3 process node covering a wide range of vertical markets. I think N3 will break tapeout records in 5 years as well.

Last but not least, TSMC announced its next-generation process technology (N2) for the masses in 2022.

Process Technology Review

With some exceptions discussed further, the supporting technology roadmap presentation was somewhat routine - this is not a bad thing but rather an indication that the previous roadmap is being successfully executed. The

roadmap update was presented twice, once as part of the technical agenda and again as part of TSMC’s platform solutions focus. Recall that TSMC specifically identified four "platforms" that receive development investments to optimize process technology products, including: mobile; high-performance computing (HPC); automotive; and Internet of Things (ultra-low power consumption). The abstract below combines the two presentations.

N7/N6

• More than 400 NTOs by the end of 2022, mainly in smartphone and CPU markets

• N6 Provides transparent migration from N7, supports IP reuse

• N6RF will be the RF solution for the upcoming WiFi 7 product

• has a N7HPC variant ( (not shown in the above image), provides about 10% performance improvement at overdrive VDD levels

• For N6, the logic unit based modules can be re-implemented in the new library to further improve performance and achieve major logic density improvements (~ 18%).

N5/N4

• In the 3rd year of production, wafer shipments using this process exceed 2 million units and will reach 150 by the end of 2022. NTO

• mobile customers are first, followed by HPC products.

• roadmap includes ongoing The N4 process enhanced

• N4P base IP is ready, the interface IP will be available in Q3 2022 (to v1.0 PDK)

• has an N5HPC variant (not shown in the above image, performance improvement is about 8%, HVM will be available in 2H22 )

N3 and N3E

• N3 will enter mass production of HVM N3E process variants starting in the second half of 2022. , high yield on standard 256Mb memory array qualification test site

• N3E Added "FinFLEX" method option, three different cell libraries optimized for different PPA requirements

Please note that N3 and N3E are somewhat different from the previous TSMC process roadmap Abnormal. N3E does not provide transparent migration of IPs from N3. The N3E product is a bit of a "correction" in that significant design rule changes from N3 were adopted to improve yields.

TSMC’s early adopter customers are driving process PPA updates on aggressive timelines, whether they are incremental compatible variants to existing baselines (e.g., N7 to N6, N5 to N4), or new nodes. The initial N3 process definition has a good NTO pipeline, but N3E will be the basis for future variants.

N2

• is based on nanosheet technology, target production date: 2025

• Compared with N3E, N2 will provide about 10-15% performance improvement (@iso-power, 0.75V) or about 25-30% work number reduction (@iso- perf, 0.75V); also note that the operating range specified in the above image is as low as 0.55V , performance and area/cost targets. As mentioned above, N3E is using different libraries to solve these problems, combined with a different number of fins that define the height of the unit. For the N2 library design, this design decision is replaced by a process technology decision regarding the number of nanosheets throughout the vertical stack (with some allowed variation in device nanosheet width). In terms of nanosheet topology, it will be interesting to see what TSMC chooses to offer N2 to cover the mobile and HPC markets. (The image below is from TSMC’s early technology demonstration at VLSI 2022, depicting 3 nanosheets.)

  

  Note: There are two emerging process technologies being adopted to reduce power transfer impedance and improve local routability – namely "Buried" power rail (BPR: buried power rail) and "backside" power distribution (BSPDN: backside power distribution). Initial investigations into delivering BPR have rapidly expanded to address roadmaps for integrating full BSPDN such as N2. However, it is easy to confuse these two acronyms.

  Sharing about special processes

  TSMC defines the following products as the "Specialty Technologies" category:

  1. Ultra-low power consumption/ultra-low leakage (using ultra-high Vt device variants)

  • Need to pay special attention to ultra-low leakage SRAM bit cell design

  • N12e in production, N6e in development (focused on very low VDD model support)

  

  Secondary (embedded) non-volatile memory

  , usually integrated with microcontroller (MCU), usually in ULP/ULL process

  , RRAM

  • requires 2 additional masks , embedded in BEOL (much lower cost than eFlash's 12 masks)

  • 10K write cycles (endurance spec), maintains ~10 at 125C In 2023,

  

  and MRAM

  • 22 MRAM have been mass-produced, with the focus on improving tolerance

  • . In 2023, 16MRAM

  for Automotive Grade 1 applications has been mass-produced. 3. Power management IC (PMIC)

  • is based on bipolar CMOS-DMOS (BCD) Device: 40BCD+, 22BCD+

  • Suitable for complex 48V/12V power domain

  • requiring extremely low device R_on

  4. High voltage applications (for example, display drivers, using N80HV or N55HV)

  5. Analog/mixed signal applications requiring unique active and passive Structure (for example, precision thin film resistors and low noise devices using N22ULL ​​and N16FFC)

  six, MEMS (for motion sensors, pressure sensors )

  seven, CMOS image sensor (CIS)

  N65 pixel size is 1.75um, N28 has a pixel size of 0.5um, transitioning to N12FFC power to support increased bandwidth requirements—for example, 2.2X area and 2.1X workers. TSMC is certifying N6RF products, which reduce power consumption by about 30-40% compared to N16RF. This will allow customers currently using N16RF to broadly maintain existing power/area targets when developing WiFi7 designs. ”

  The figure below illustrates how these specialized technologies become fundamental components of platform products such as smartphones and automotive products. The characteristic process nodes used for these applications are also shown.

  Although the focus of smartphone development tends to be on the main application processor, the table below highlights the extremely diverse requirements for specialized technology products and their associated functions. In the automotive world, the transition to “region control” architecture will require a new set of automotive ICs.

  

  N3E and FinFLEX

  TSMC specifically emphasized the newly released FinFLEX method. TSMC said that FinFLEX will provide full node expansion of N5.

  

  As FinFET technology nodes expand (i.e. from N16 to N10 to N7 to N5), the fin profile and drive current per micron improve significantly. Standard cell library designs have evolved to include fewer pFET and nFET fins that define the cell height (specified in terms of the number of horizontal metal routing tracks). As shown above, the N5 library uses a 2-2 fin definition - that is, 2 pFET fins and 2 nFET fins to define the cell height. (N16/N12 uses the 3-3 configuration.) The library definition for

  N3E faces several issues. The scale of performance improvements in pFET and nFET devices is not the same. And, mobile and HPC platform applications are increasingly different in terms of their PPA (and cost) targets. Mobile products focus on circuit density to integrate more functions and/or reduce power consumption, while not requiring high performance improvements. HPC is more focused on maximizing performance.

  Therefore, N3E will provide three libraries, as shown in the picture above:

  • 2:1 Ultra-low power library (track height is defined by 2 pFET:1 nFET)

  • 2:2 High-efficiency library

  • 3:2 Performance library

  The picture below is from TSMC The FinFLEX website, illustrates this concept.

  

  Now, integrating multiple libraries on a single SoC is nothing new. Over the years, processor companies have developed unique "datapath" and "control logic" library products targeting different goals: cell height, circuit performance, routability (i.e. maximum cell area utilization) and different logic products (e.g. , wide AND - OR gate for datapath multiplexing ). However, the physical implementation of an SoC design using multiple libraries relies on consistent libraries for each design block.

  Although the TSMC picture above also depicts one library per block, the FinFLEX approach is unique in that multiple libraries and multiple track heights will be mixed in a single block. Will support 2:1 plus 2:2 bank and 2:2 plus 3:2 bank combinations.

  TSMC said, "Enable different cell heights in a block (in separate rows) to optimize PPA. FinFLEX in N3E combines new design rules, new layout techniques, and significant changes to the EDA implementation flow."

  will definitely have more information on FinFLEX and general design flow changes. On the other hand, new methods are needed:

  1. Floorplanning

  • Planning the percentage combination of two different row heights for a block

  • The target utilization percentage of cells in different library rows to achieve routability (including for decap fill open cells)

  • PDN "reduction" approach for blocks with significant percentage of low power cells

  • Number of floorplanning iterations (via physical synthesis) of a block to achieve closure For the timing of high-load signals, synthesis will typically update the cell assignments in the library to the next higher drive strength—for example, NAND2_1X to NAND2_2X.

    For FinFLEX, the second library provides additional options - for example, whether an update to NAND2_1X_2:2 uses NAND2_2X_2:2 or NAND2_1X_3:2. However, if you choose the latter, you will need to "rebalance" the new units to different rows in the block plan. The performance of these choices and the effective changes in input/output line loading are difficult to estimate during physical synthesis (not to mention that the specific RDLY and FDLY latency transitions of output ramp-up vs. ramp-down for different library cells may scale differently).

    The cell selection options become more complex when considering specific flop cells to be used, taking into account not only differences in clock-to-Q latency, but also setup and hold time characteristics and input clock loading. When would it be better to use different drive strengths for the individual trigger bits in the register in the same library (and place them locally) versus rebalancing the register bits to rows corresponding to different library selections?

    3. Sub-block-level IP integration

    Blocks usually contain many small hard-core IP macros, such as register files (usually provided by a register file generator). How will these hard IP macros be designed and placed due to the uneven height of the cell rows across a single block?

    4. Timing/power optimization during physical design

    Similar to the physical synthesis block construction option, unit selection will face difficult decisions during the timing and power optimization steps of the physical design flow. For example, if a unit could reduce its assigned drive strength to save power while still meeting timing, would a change in bank selection be considered, thereby rebalancing the row? Will a change in cell position negate optimization?

    5. Last but not least, will enabling N3E FinFLEX incur new EDA license fees?

    (A few years ago, the CAD department manager at my previous employer went big on the license cost adder to implement place and route for multi-mode requirements. Given the large EDA investment required to support FinFLEX, history may repeat itself with additional licenses Feature Cost.)

    The FinFLEX approach certainly offers some interesting options. It will be interesting to see how this approach evolves.

    Analog Design Migration Automation

    Finally, TSMC briefly highlighted their ongoing work in assisting designers in migrating analog/mixed-signal circuits and layouts to newer process nodes.

    Specifically, TSMC has defined a set of "analog cells" capable of taking existing schematics, remapping to new nodes, evaluating circuit optimization and migrating layouts, including automatic placement and (PG + signal) routing. The definition of the simulation unit library of

    N5/N4 and N3E has been completed, and N7/N6 will be supported in the future. TSMC showed an example of an operational transimpedance amplifier (OTA) going through the migration process.

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